component

sit1042at

Public Made by Adom

by adom

SIT CAN Transceivers, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentinterfacesit1042at
Overview Files Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Contents

README

markdown

SIT1042AT

SIT · CAN Transceivers · SOP-8

SIT1042AT from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input from the CAN controller. Logic low drives a dominant bit onto CANH/CANL; logic high releases the bus to the recessive state. Internally pulled up to VIO (or VCC on this variant). Includes a dominant time-out to prevent bus lock-up if TXD is stuck low.
2 GND power_in Device ground reference (0 V) for the transceiver and bus drivers.
3 VCC power_in Main supply for the transceiver and CAN line drivers. Operating range 4.5 V to 5.5 V (absolute max −0.3 V to 7 V). Includes VCC under-voltage protection.
4 RXD output Receive data output to the CAN controller. Reports the state of the differential bus: low = dominant, high = recessive. Push-pull driver referenced to VCC on this variant (to VIO on the /3 variant).
5 N.C. unconnected No internal connection on the SIT1042AT variant. On the SIT1042AT/3 variant this pin is VIO (I/O level-shift supply for 3.3 V MCU compatibility). Leave floating or tie to GND.
6 CANL bidirectional Low-side CAN bus line. Driven low (dominant) or held at ~0.5·VCC (recessive) with respect to CANH. Bus-fault tolerant to ±70 V; differential input resistance 19-52 kΩ (typ 30 kΩ).
7 CANH bidirectional High-side CAN bus line. Driven high (dominant) or held at ~0.5·VCC (recessive) with respect to CANL. Bus-fault tolerant to ±70 V.
8 STB input Mode-select input. Logic low = high-speed (normal) mode with transmitter and receiver active; logic high = low-power standby mode (transmitter disabled, low-power receiver monitors bus for wake-up). Internally pulled up to VIO/VCC.

Key specifications

Parameter Value
Manufacturer SIT
Package SOP-8
Category Interface
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SIT1042AT
  • SIT1042AT/3

CAD (KiCad official)

  • Symbol: SIT1042AT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: sit1042at-etched.step / sit1042at-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sit1042at.step / sit1042at.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SIT datasheet (20 pp, sha256 3b7b3ad8c24a147c, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF