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SIR880DP-VB

Public Made by Adom

by adom

VBsemi Elec MOSFETs, DFN5x6-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SIR880DP-VB

VBsemi Elec · MOSFETs · DFN5x6-8

SIR880DP-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET (pin 1, marked with dot); VDS max 80 V, continuous source-drain diode current 60 A at TC = 25 °C.
2 S passive Source terminal of the N-channel MOSFET, connected in parallel with the other source pins.
3 S passive Source terminal of the N-channel MOSFET, connected in parallel with the other source pins.
4 G input Gate terminal; gate-source voltage limit is ±20 V, with threshold VGS(th) of 1.2 V min to 2.8 V max at ID = 250 μA.
5 D passive Drain terminal; drain-source voltage rating 80 V, continuous drain current 60 A (package limited) at TC = 25 °C.
6 D passive Drain terminal, connected in parallel with the other drain pins.
7 D passive Drain terminal, connected in parallel with the other drain pins.
8 D passive Drain terminal, connected in parallel with the other drain pins.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package DFN5x6-8
Category Triode/MOS Tube/Transistor
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage VDS 80 V VGS = 0 V, ID = 250 μA 2
Gate-Source Threshold Voltage VGS(th) 1.2 2.8 V VDS = VGS, ID = 250 μA 2
Gate-Source Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current IDSS 1 μA VDS = 80 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS 10 μA VDS = 80 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) 30 A VDS ≥ 5 V, VGS = 10 V 2
Total Gate Charge Qg 57 86 nC VDS = 40 V, VGS = 10 V, ID = 20 A 2
Total Gate Charge Qg 42 63 nC VDS = 40 V, VGS = 7.5 V, ID = 20 A 2
Output Charge Qoss 70 105 nC VDS = 40 V, VGS = 0 V 2
Gate Resistance Rg 0.3 0.95 1.9 Ω f = 1 MHz 2
Rise Time tr 12 24 ns VDD = 40 V, RL = 2 Ω, ID ≅ 20 A, VGEN = 10 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 34 68 ns VDD = 40 V, RL = 2 Ω, ID ≅ 20 A, VGEN = 10 V, Rg = 1 Ω 2
Rise Time tr 15 30 ns VDD = 40 V, RL = 2 Ω, ID ≅ 20 A, VGEN = 7.5 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 32 64 ns VDD = 40 V, RL = 2 Ω, ID ≅ 20 A, VGEN = 7.5 V, Rg = 1 Ω 2
Continuous Source-Drain Diode Current IS 60 A TC = 25 °C 2
Pulse Diode Forward Current ISM 100 A 2
Body Diode Voltage VSD 0.73 1.1 V IS = 5 A 2
Body Diode Reverse Recovery Time trr 53 105 ns IF = 20 A, dI/dt = 100 A/μs, TJ = 25 °C 2
Body Diode Reverse Recovery Charge Qrr 65 130 nC IF = 20 A, dI/dt = 100 A/μs, TJ = 25 °C 2
Drain-Source Voltage VDS 80 V TA = 25 °C 1
Gate-Source Voltage VGS -20 20 V TA = 25 °C 1
Continuous Drain Current ID 60 A TC = 25 °C, TJ = 150 °C, package limited 1
Continuous Drain Current ID 23.8 A TA = 25 °C, t = 10 s 1
Continuous Drain Current ID 19 A TA = 70 °C, t = 10 s 1
Pulsed Drain Current IDM 100 A t = 300 μs 1
Continuous Source-Drain Diode Current IS 60 A TC = 25 °C 1
Continuous Source-Drain Diode Current IS 5.6 A TA = 25 °C, t = 10 s 1
Single Pulse Avalanche Current IAS 35 A L = 0.1 mH 1
Single Pulse Avalanche Energy EAS 61 mJ L = 0.1 mH 1
Maximum Power Dissipation PD 104 W TC = 25 °C 1
Maximum Power Dissipation PD 66.6 W TC = 70 °C 1
Maximum Power Dissipation PD 6.25 W TA = 25 °C, t = 10 s 1
Maximum Power Dissipation PD 4 W TA = 70 °C, t = 10 s 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Soldering Peak Temperature 260 °C 1
Junction-to-Ambient Thermal Resistance RthJA 15 20 °C/W t ≤ 10 s 1
Junction-to-Case (Drain) Thermal Resistance RthJC 0.9 1.2 °C/W Steady State 1
Drain-Source On-State Resistance RDS(on) 0.0048 Ω VGS = 10 V, ID = 20 A 2
Drain-Source On-State Resistance RDS(on) 0.005 Ω VGS = 7.5 V, ID = 20 A 2
Drain-Source On-State Resistance RDS(on) 0.0064 Ω VGS = 4.5 V, ID = 15 A 2
Forward Transconductance gfs 68 S VDS = 10 V, ID = 20 A 2
Input Capacitance Ciss 2800 pF VDS = 40 V, VGS = 0 V, f = 1 MHz 2
Output Capacitance Coss 1100 pF VDS = 40 V, VGS = 0 V, f = 1 MHz 2
Reverse Transfer Capacitance Crss 93 pF VDS = 40 V, VGS = 0 V, f = 1 MHz 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper d. The DFN 5X x6 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation 1

CAD (KiCad official)

  • Symbol: SIR880DP-VB
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN5x6-8 (KiCad packages3D, STEP)
  • 3D model files: sir880dp-vb-etched.step / sir880dp-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sir880dp-vb.step / sir880dp-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (8 pp, sha256 9fbf68eb09428252, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF