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SIP32433ADN-T1E4

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Vishay Intertech Power Distribution Switches, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SIP32433ADN-T1E4

Vishay Intertech · Power Distribution Switches · DFN-10(3x3)

SIP32433ADN-T1E4 from Vishay Intertech, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Power switch input pin; two VIN pins are fused inside the package.
2 VIN power_in Power switch input pin; two VIN pins are fused inside the package.
3 SS passive A capacitor from this pin to GND sets the output voltage slew rate.
4 EN / UVLO input Active high switch control input with VTHL < 0.3 V and VTHH > 1.4 V.
5 ILIM / IMON bidirectional A resistor from this pin to GND sets the overload and short-circuit current limit; the pin can also be used for current reporting, referring to the voltage developed over the current limit setting resistor.
6 GND power_in Ground pin.
7 OVP input Input for setting the programmable overvoltage protection threshold; an overvoltage event turns off the internal FET and asserts FLT to indicate the overvoltage fault.
8 PGD output Open-drain power-good output that is asserted when VOUT is 95 % VIN and none of the OT, OC, or OV faults are triggered.
9 VOUT power_out Power switch output pin; two VOUT pins are fused inside the package.
10 VOUT power_out Power switch output pin; two VOUT pins are fused inside the package.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package DFN-10(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage (VIN) absolute maximum, reference to GND VIN -0.3 28 V Reference to GND 2
Output voltage (VOUT) absolute maximum, reference to GND VOUT -0.3 28 V Reference to GND 2
Output voltage (VOUT) transient VOUT -5 V -5 V for +5 s 2
EN voltage absolute maximum EN -0.3 24 V Reference to GND 2
OVP pin absolute maximum OVP -0.3 6 V Reference to GND 2
SS pin absolute maximum SS -0.3 6 V Reference to GND 2
ILIM pin absolute maximum ILIM -0.3 6 V 2
PGD pin absolute maximum PGD -0.3 6 V 2
Maximum continuous switch current 3.5 A 2
ESD rating HBM -1 1 kV HBM 2
ESD rating CDM -1 1 CDM 2
Latch up current 100 mA Per JESD78E, Class II 2
Operating junction temperature (absolute maximum) TJ -40 150 °C 2
Storage temperature -65 150 °C 2
Input voltage (VIN) recommended operating range VIN 2.8 22 V 2
Operating junction temperature recommended range TJ -40 125 °C 2
Power input voltage operating range VIN 2.8 28 V Operating input voltage range 3
Quiescent current (on) IQ(ON) 250 340 μA EN = 1.8 V, VIN = 2.8 V to 28 V, VOUT open 3
Shutdown current IQ(SD) 0.6 5 μA VIN = 2.8 V to 28 V, EN = 0 V, TA = 25 °C 3
Switch VOUT leakage IUVLO_OUT -100 100 nA 3
Switch VIN leakage IUVLO_IN 5 μA 3
OVP threshold VOVP 1.14 1.2 1.26 V VIN = 12 V, OVP rising 3
OVP hysteresis OVPHST 60 105 140 mV 3
OVP leakage IOVP 40 100 nA VOVP = 1.2 V on the pin, TA = 25 °C 3
IN pin internal fixed OVP INOVP 22.1 24 25.6 V TA = 25 °C 3
EN / UVLO leakage -0.25 0.25 μA VEN = 1.2 V 3
Current limit accuracy (RSET = 4.1 k) IOCP 1.39 1.5 1.6 A VIN - VOUT = 1 V, RSET = 4.1 k 3
Current limit accuracy (RSET = 1.8 k) IOCP 3.32 3.5 3.68 A VIN - VOUT = 1 V, RSET = 1.8 k 3
Current limit setting range 0.25 4.5 A 3
Current limit hold-up time tILIM 4 6 8 ms Current limiting timeout, if no OTP 3
On resistance (TJ = 25 °C) RDS(ON) 78 100 mΩ VIN = 3 V to 22 V, IOUT = 1 A, TJ = 25 °C 3
On resistance (TJ = 85 °C) RDS(ON) 130 mΩ VIN = 3 V to 22 V, IOUT = 1 A, TJ = 85 °C 3
Output leakage at switch off 5 A VIN = 28 V, VEN = 0 V, VOUT = 0 V, sourcing 3
PGD pull-down resistance RPG 5.2 10 Ω VIN = 5 V, output pin = 0.1 V 3
PGD leakage IPG 0.01 1 μA Biased with 5 VDC 3
OVP off time tOVP 0.3 1 μs RL = 100, CL = 0 μF, OVP steps from 1 V to 1.4 V; measured to VOUT = 0.9 x VIN 3
Flag reporting delay 2 PGD pull up to 5 V through a 100 k; delay from OVP pin voltage step to PGD below 0.5 V 3
Thermal resistance (junction to ambient) thJA 44.8 °C/W 2

CAD (KiCad official)

  • Symbol: SIP32433ADN-T1E4
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
  • 3D model files: sip32433adn-t1e4-etched.step / sip32433adn-t1e4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sip32433adn-t1e4.step / sip32433adn-t1e4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (22 pp, sha256 33d8d931128752b5, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF