component
SIP12109DMP-T1-GE4
Public Made by Adomby adom
Vishay Intertech DC-DC Converters, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 10d ago |
| viewers | 10d ago |
| package.json | 10d ago |
| page.json | 10d ago |
| README.md | 10d ago |
| sip12109dmp-t1-ge4-etched.glb | 10d ago |
| sip12109dmp-t1-ge4-etched.step | 10d ago |
| sip12109dmp-t1-ge4-hero.glb | 10d ago |
| sip12109dmp-t1-ge4-hero.overlay.json | 10d ago |
| sip12109dmp-t1-ge4.glb | 10d ago |
| sip12109dmp-t1-ge4.kicad_mod | 10d ago |
| sip12109dmp-t1-ge4.kicad_sym | 10d ago |
| sip12109dmp-t1-ge4.lbr | 10d ago |
| sip12109dmp-t1-ge4.step | 10d ago |
SIP12109DMP-T1-GE4
Vishay Intertech · DC-DC Converters · QFN-16-EP(3x3)
SIP12109DMP-T1-GE4 from Vishay Intertech, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply voltage for power MOS, VIN = 4.5 V to 15 V. |
| 2 | VCC | power_out | Internal regulator output (4.5 V to 5.5 V); tie VCC to VIN when VIN is < 5.5 V. |
| 3 | AGND | power_in | Analog ground. |
| 4 | RON | passive | An external resistor between RON and AGND sets the switching on time. |
| 5 | COMP | passive | Connect to an external RC network for loop compensation and droop function. |
| 6 | VFB | input | Feedback voltage, 0.6 V (typ.); use a resistor divider between VOUT and AGND to set the output voltage. |
| 7 | SS | passive | An external capacitor between SS and AGND sets the soft start time. |
| 8 | EN | input | Enable pin; pull above 1.5 V to enable and below 0.4 V to disable the part, do not float this pin. |
| 9 | PGOOD | output | Power good output, open drain; pull high up to 5 V through a 10K resistor. |
| 10 | LX | passive | Switching node, inductor connection point. |
| 11 | LX | passive | Switching node, inductor connection point. |
| 12 | LX | passive | Switching node, inductor connection point. |
| 13 | BOOT | passive | Bootstrap pin; connect a capacitor of at least 100 nF from BOOT to LX to develop the floating supply for the high-side gate drive. |
| 14 | PGND | power_in | Power ground. |
| 15 | PGND | power_in | Power ground. |
| 16 | VIN | power_in | Input supply voltage for power MOS, VIN = 4.5 V to 15 V. |
| 17 | PGND | power_in | Exposed pad, power ground (listed as PAD in the pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | QFN-16-EP(3x3) |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN reference to PGND | VIN | -0.3 | 16 | V | Reference to PGND | 2 | |
| VCC reference to AGND | VCC | -0.3 | 6 | V | Reference to AGND | 2 | |
| LX reference to PGND | LX | -0.3 | 16 | V | Reference to PGND | 2 | |
| LX (AC) | LX | 17 | V | 100 ns | 2 | ||
| Boot | -0.3 | V | 2 | ||||
| AGND to PGND | -0.3 | 0.3 | V | 2 | |||
| All logic inputs | -0.3 | V | Reference to AGND | 2 | |||
| Maximum power dissipation | 3.4 | W | Ambient temperature = 25 °C | 2 | |||
| Maximum power dissipation | 1.3 | W | Ambient temperature = 100 °C | 2 | |||
| Max. operating junction temperature | -40 | 150 | °C | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Electrostatic discharge protection HBM | 2 | kV | HBM | 2 | |||
| VIN power input voltage range | VIN | 4.5 | 15 | V | 3 | ||
| VCC | VCC | 4.5 | 5.5 | V | 3 | ||
| LX | LX | -1 | 15 | V | 3 | ||
| VOUT | VOUT | 0.6 | 5.5 | V | 3 | ||
| Recommended ambient temperature | -40 | 85 | °C | 3 | |||
| Operating junction temperature | -40 | 125 | °C | 3 | |||
| Power input voltage range | VIN | 4.5 | 15 | V | Note 1 | 3 | |
| VCC regulator voltage | VCC | 4.5 | 5 | 5.5 | V | 3 | |
| Shutdown current | IVIN_SHDN | 5 | 8 | μA | EN = 0 V | 3 | |
| VCC UVLO threshold | VCC_UVLO | 2.3 | 2.55 | 2.8 | V | VCC rising | 3 |
| Feedback reference voltage | VFB | 0.596 | 0.6 | 0.604 | V | TA = 25 °C | 3 |
| Feedback reference voltage | VFB | 0.594 | 0.6 | 0.606 | V | TA = -40 °C to +85 °C | 3 |
| VFB input bias current | IFB | 2 | 200 | nA | 3 | ||
| On-time | tON | 100 | 135 | 170 | ns | Ron = 75 k | 3 |
| Minimum off-time | tOFF_MIN | 145 | 200 | 255 | ns | 3 | |
| Soft start current | ISS | 3 | 5 | 7 | μA | 3 | |
| High-side on resistance | RON_HS | 45 | 67 | mΩ | VGS = 5 V | 3 | |
| Low-side on resistance | RON_LS | 27 | 41 | mΩ | 3 | ||
| Over current limit | IOCP | 4 | 5 | 6 | A | Inductor valley current | 3 |
| Power good on resistance | RON_PGOOD | 30 | 60 | Ω | 3 | ||
| Logic high level | VEN_H | 1.5 | V | 3 | |||
| Logic low level | VEN_L | 0.4 | V | 3 | |||
| Junction to ambient thermal impedance | RthJA | 36.3 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
SIP12109DMP-T1-GE4 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
sip12109dmp-t1-ge4-etched.step/sip12109dmp-t1-ge4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sip12109dmp-t1-ge4.step/sip12109dmp-t1-ge4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (16 pp, sha256
de012f14e3091551, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).