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SiLM5350MDBCA-DG

Public Made by Adom

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Sillumin Isolators - Gate Drivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SiLM5350MDBCA-DG

Sillumin · Isolators - Gate Drivers · SOP-8

SiLM5350MDBCA-DG from Sillumin, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Input-side supply voltage, recommended 3V to 18V (absolute maximum 20V), with VCC1 UVLO rising threshold 2.7V typ.
2 IN+ input Noninverting voltage control input, pulled low internally (180 kΩ typ pull-down) if left open, with input range -5V to 18V recommended.
3 IN- input Inverting voltage control input, pulled high internally (180 kΩ typ pull-up) if left open, with input range -5V to 18V recommended.
4 GND1 power_in Input-side ground, reference for VCC1 and the IN+/IN- inputs.
5 VCC2 power_in Positive output supply voltage, VCC2-VEE2 recommended 13.5V to 30V for the 12.5V UVLO option (MDBCA), with UVLO rising 12.5V typ and falling 11.5V typ.
6 OUT output Gate driver output with 10A peak source and 10A peak sink current, swinging rail-to-rail between VEE2 and VCC2.
7 CLAMP input Active Miller clamp input used to prevent false turn-on of the power switches, activating when the pin falls below the 2V typ threshold relative to VEE2 (10A clamp current).
8 VEE2 power_in Negative output supply voltage (output-side ground reference), with VCC2-VEE2 absolute maximum of 35V.

Key specifications

Parameter Value
Manufacturer Sillumin
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC1 UVLO Rising VUVLO_VCC1_R 2.55 2.7 2.85 V 13
VCC1 UVLO Falling VUVLO_VCC1_F 2.35 2.5 2.65 V 13
VCC2 UVLO Rising, 12.5V UVLO version VUVLO_VCC2_R 11.5 12.5 13.5 V VCC2-VEE2, 12.5V UVLO Version 13
VCC2 UVLO Falling, 12.5V UVLO version VUVLO_VCC2_F 10.5 11.5 12.5 V VCC2-VEE2, 12.5V UVLO Version 13
VCC1 Input Supply Voltage (electrical) VCC1 3 18 V 13
ICC1 Quiescent Current ICC1 2 2.5 mA VIN+ = 0V, VIN- = VCC1 13
ICC1 Operation Current ICC1 2.6 3.3 mA CLOAD=1nF, fsw= 50kHz, (50% Duty Cycle) 13
ICC2 Quiescent Current ICC2 1.4 2.1 mA VIN+ = 0V, VIN- = VCC1 14
ICC2 Operation Current ICC2 2.7 3.5 mA CLOAD=1nF, fsw= 50kHz, (50% Duty Cycle) 14
High Level Output Voltage VOH 8 15 mV IO=-20mA 14
Low Level Output Voltage VOL 8 15 mV IO=20mA 14
Active pulldown voltage on OUT VOUTSD 1.8 2.5 V IOUT=1A, VCC2 Open 14
Clamp low level voltage VCLAMP 7 13 mV ICLAMP=20mA 14
Clamp threshold voltage VCLAMP-TH 1.8 2 2.2 V 14
High Level Input Threshold Voltage at IN+ and IN- VIH 2 V 13
Low Level Input Threshold Voltage at IN+ and IN- VIL 0.8 V 13
Propagation delay, Low to High tPLH 80 130 ns CLOAD=1nF, fsw=20kHz, (50% Duty Cycle) 15
Propagation delay, High to Low tPHL 80 130 ns CLOAD=1nF, fsw=20kHz, (50% Duty Cycle) 15
Pulse Width Distortion tPWD 40 ns CLOAD=1nF, fsw=20kHz, (50% Duty Cycle) 15
Propagation Delay Difference Between Any Two Parts tPDD 40 ns CLOAD=1nF, fsw=20kHz, (50% Duty Cycle) 15
Turn on rise time tr 15 ns CLOAD=1nF 15
Turn off fall time tf 15 ns CLOAD=1nF 15
Output High Level CMTI CMTIH 150 200 kV/us VCM=1000V, VCC=15V, TA=25°C 15
Output Low Level CMTI CMTIL 150 200 kV/us VCM=1000V, VCC=15V, TA=25°C 15
VCC1 UVLO Hysteresis VUVLO_VCC1_HYS 0.2 V 13
VCC2 UVLO Hysteresis, 12.5V version VUVLO_VCC2_HYS 1 V VCC2-VEE2, 12.5V UVLO Version 13
Pull down Resistance on IN+ RPD 180 kΩ 13
Pull up Resistance on IN- RPU 180 kΩ 13
Peak Source Current IOH 10 A 14
Peak Sink Current IOL 10 A 14
Clamp low level current ICLAMP 10 A 14
VCC1 UVLO Recovery Delay tUVLO_REC1 12 us VCC1 Rising from 0V to 5V 15
VCC2 UVLO Recovery Delay tUVLO_REC2 20 us VCC2 Rising from 0V to 15V 15
Input Supply Voltage (abs max) VCC1 -0.3 20 V 9
Input Signal Voltage (abs max) VIN+, VIN- -7 20 V 9
Driver supply voltage (abs max) VCC2-VEE2 -0.3 35 V 9
Internal clamping voltage CLAMP-VEE2 (abs max) CLAMP-VEE2 -0.3 V Min printed as VEE2-0.3, max VCC2+0.3 9
Junction temperature (abs max) TJ -40 150 °C 9
Storage temperature TS -55 150 °C 9
Input Supply Voltage (recommended) VCC1 3 18 V 9
Input Signal Voltage (recommended) VIN+, VIN- -5 18 V 9
Driver supply voltage (12.5V UVLO option) VCC2-VEE2 13.5 30 V 12.5V UVLO option 9
Ambient temperature TA -40 125 °C 9
ESD HBM VESD 4000 V HBM 9
ESD CDM VESD 1500 V CDM 9
Junction to ambient thermal resistance, SOP8 RθJA 108.7 °C/W SOP8 9
Junction to case (top) thermal resistance, SOP8 RθJC 43.1 °C/W SOP8 9

CAD (KiCad official)

  • Symbol: SiLM5350MDBCA-DG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: silm5350mdbca-dg-etched.step / silm5350mdbca-dg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); silm5350mdbca-dg.step / silm5350mdbca-dg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sillumin datasheet (24 pp, sha256 c70745f1c5da93fd, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF