SII9293CNUC

Lattice · Video Interface ICs · QFN-72-EP(10x10)

SII9293CNUC from Lattice, in a QFN-72-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDH	power_in	Receiver termination 3.3 V analog supply input (3.14-3.46 V), connect to an external 3.3 V regulator or VCC33_OUT.
2	RXCN	input	TMDS HDMI clock pair negative input.
3	RXCP	input	TMDS HDMI clock pair positive input.
4	RX0N	input	TMDS HDMI Channel 0 negative input or MHL input port data pair; other HDMI channels and clock are unused in MHL mode.
5	RX0P	input	TMDS HDMI Channel 0 positive input or MHL input port data pair; other HDMI channels and clock are unused in MHL mode.
6	RX1N	input	TMDS HDMI Channel 1 negative input.
7	RX1P	input	TMDS HDMI Channel 1 positive input.
8	RX2N	input	TMDS HDMI Channel 2 negative input.
9	RX2P	input	TMDS HDMI Channel 2 positive input.
10	VDD	power_in	Digital power, 1.0 V (0.95-1.05 V).
11	GPIO0_CI2CA	bidirectional	General purpose I/O 0 or CI2CA; defaults to input and is sampled once at reset to select the local I2C address range, LVTTL Schmitt, 5 V tolerant.
12	GPIO1	bidirectional	General purpose I/O 1, LVTTL Schmitt, 5 V tolerant.
13	CSDA	bidirectional	Local I2C data, true open drain, 5 V tolerant, requires external pull-up to 3.3 V.
14	CSCL	input	Local I2C clock, true open drain, 5 V tolerant, requires external pull-up resistor to 3.3 V.
15	INT	output	Active-low open-drain interrupt output to host controller, 5 V tolerant, requires external pull-up resistor.
16	TMODE	output	Test mode enable, open drain, 5 V tolerant; pull down for normal operation.
17	VCC33_OUT	power_out	Internal 3.3 V regulator output, requires 10 µF capacitor to ground, maximum output current 30 mA.
18	RESET_N	input	Active-low external reset, Schmitt, 5 V tolerant, internal pull-up; can be left open when not required.
19	DSDA	bidirectional	DDC I2C data, open drain, 5 V tolerant, carries HDCP KSV, An and Ri; drives low when only SBVCC5V or RPWR5V is present; DDC master for EDID EEPROM in MHL mode.
20	DSCL	bidirectional	DDC I2C clock, open drain, 5 V tolerant, carries HDCP exchange; drives low when only SBVCC5V or RPWR5V is present; DDC master for EDID EEPROM in MHL mode.
21	CBUS_HPD	bidirectional	MHL mode: CBUS control signal at 1.8 V level; HDMI mode: HPD output; 5 V tolerant.
22	RPWR5V	power_in	5 V port detection input (4.3-5.5 V) from HDMI +5 V or MHL VBUS; needs 10 Ω series resistor, 5.1 kΩ pull-down and at least 1 µF to ground.
23	SBVCC5V	power_in	Local 5 V power input (4.3-5.5 V), required if no RPWR5V input; needs 10 Ω series resistor.
24	MHL_CD	input	MHL cable detect input, LVTTL Schmitt, 5 V tolerant.
25	CBUS_OE	output	LVTTL output enable for CBUS output.
26	CEC_A	bidirectional	HDMI-compliant CEC I/O, 5 V tolerant, with internal pull-up resistor, connects to the CEC signal of all HDMI connectors.
27	VDD	power_in	Digital power, 1.0 V (0.95-1.05 V).
28	GNDIO	power_in	Digital I/O ground.
29	VDDIO	power_in	Digital I/O power, 3.3 V (3.14-3.46 V).
30	SD0_SPDIF	output	LVTTL I2S/TDM serial data or S/PDIF audio output.
31	WS	output	LVTTL I2S word select or TDM frame start (FS) signal.
32	SCK	output	LVTTL I2S or TDM serial clock.
33	MCLK	output	LVTTL audio output master clock.
34	VSYNC	output	LVTTL vertical sync output.
35	DE	output	LVTTL data enable output.
36	HSYNC	output	LVTTL horizontal sync output.
37	Q0	output	24-bit output pixel data bus bit 0, LVTTL, configurable format, can be put in high impedance.
38	Q1	output	24-bit output pixel data bus bit 1, LVTTL, configurable format, can be put in high impedance.
39	Q2	output	24-bit output pixel data bus bit 2, LVTTL, configurable format, can be put in high impedance.
40	Q3	output	24-bit output pixel data bus bit 3, LVTTL, configurable format, can be put in high impedance.
41	Q4	output	24-bit output pixel data bus bit 4, LVTTL, configurable format, can be put in high impedance.
42	Q5	output	24-bit output pixel data bus bit 5, LVTTL, configurable format, can be put in high impedance.
43	Q6	output	24-bit output pixel data bus bit 6, LVTTL, configurable format, can be put in high impedance.
44	Q7	output	24-bit output pixel data bus bit 7, LVTTL, configurable format, can be put in high impedance.
45	GNDIO	power_in	Digital I/O ground.
46	ODCK	output	LVTTL output data clock.
47	VDDIO	power_in	Digital I/O power, 3.3 V (3.14-3.46 V).
48	Q8	output	24-bit output pixel data bus bit 8, LVTTL, configurable format, can be put in high impedance.
49	Q9	output	24-bit output pixel data bus bit 9, LVTTL, configurable format, can be put in high impedance.
50	Q10	output	24-bit output pixel data bus bit 10, LVTTL, configurable format, can be put in high impedance.
51	Q11	output	24-bit output pixel data bus bit 11, LVTTL, configurable format, can be put in high impedance.
52	Q12	output	24-bit output pixel data bus bit 12, LVTTL, configurable format, can be put in high impedance.
53	Q13	output	24-bit output pixel data bus bit 13, LVTTL, configurable format, can be put in high impedance.
54	Q14	output	24-bit output pixel data bus bit 14, LVTTL, configurable format, can be put in high impedance.
55	Q15	output	24-bit output pixel data bus bit 15, LVTTL, configurable format, can be put in high impedance.
56	VDD	power_in	Digital power, 1.0 V (0.95-1.05 V).
57	Q16	output	24-bit output pixel data bus bit 16, LVTTL, configurable format, can be put in high impedance.
58	Q17	output	24-bit output pixel data bus bit 17, LVTTL, configurable format, can be put in high impedance.
59	Q18	output	24-bit output pixel data bus bit 18, LVTTL, configurable format, can be put in high impedance.
60	Q19	output	24-bit output pixel data bus bit 19, LVTTL, configurable format, can be put in high impedance.
61	GNDIO	power_in	Digital I/O ground.
62	VDDIO	power_in	Digital I/O power, 3.3 V (3.14-3.46 V).
63	Q20	output	24-bit output pixel data bus bit 20, LVTTL, configurable format, can be put in high impedance.
64	Q21	output	24-bit output pixel data bus bit 21, LVTTL, configurable format, can be put in high impedance.
65	Q22	output	24-bit output pixel data bus bit 22, LVTTL, configurable format, can be put in high impedance.
66	Q23	output	24-bit output pixel data bus bit 23, LVTTL, configurable format, can be put in high impedance.
67	XTALIN	input	Crystal clock input, LVTTL, 5 V tolerant; can be driven by a clock (XTALOUT unconnected) or connected through a crystal to XTALOUT.
68	XTALOUT	output	LVTTL crystal clock output.
69	XTALGND	power_in	Crystal ground.
70	XTALVCC33	power_in	Crystal power, 3.3 V (3.14-3.46 V).
71	APLLVDD	power_in	Analog PLL power, 1.0 V (0.95-1.05 V).
72	AVDD	power_in	Analog core VDD, 1.0 V (0.95-1.05 V).
73	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Lattice
Package	QFN-72-EP(10x10)
Category	Interface ICs
Pins	73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Primary On-chip Regulator Supply Voltage (abs max)	SBVCC5V	-0.3		5.7	V		15
Supply Voltage (abs max)	RPWR5V	-0.3		5.7	V		15
Digital Core Supply Voltage (abs max)	VDD	-0.3		1.25	V		15
Analog Core Supply Voltage (abs max)	AVDD	-0.3		1.25	V		15
Analog PLL Supply Voltage (abs max)	APLLVDD	-0.3		1.25	V		15
Digital I/O Power Voltage (abs max)	VDDIO	-0.3		4	V		15
TMDS I/O Supply Voltage (abs max)	VDDH	-0.3		4	V		15
ACR PLL Crystal Oscillator Supply Voltage (abs max)	XTALVCC33	-0.3		4	V		15
Input Voltage (abs max)	VI	-0.3			V	max VDDIO + 0.3 V	15
Output Voltage (abs max)	VO	-0.3			V	max VDDIO + 0.3 V	15
Junction Temperature	TJ			125	C		15
Storage Temperature	TSTG	-65		150	C		15
Primary On-chip Regulator Supply Voltage	SBVCC5V	4.3	5	5.5	V		16
Supply Voltage	RPWR5V	4.3	5	5.5	V		16
Digital Core Supply Voltage	VDD	0.95	1	1.05	V		16
Analog Core Supply Voltage	AVDD	0.95	1	1.05	V		16
Analog PLL Supply Voltage	APLLVDD	0.95	1	1.05	V		16
Digital I/O Power Voltage	VDDIO	3.14	3.3	3.46	V		16
TMDS I/O Supply Voltage	VDDH	3.14	3.3	3.46	V		16
ACR PLL Crystal Oscillator Supply Voltage	XTALVCC33	3.14	3.3	3.46	V		16
3.3 V Supply Voltage Noise	VDD33N			100	mVP-P		16
Ambient Temperature (with power applied)	TA	-20	25	85	C		16
Ambient Thermal Resistance (Theta JA)	θja			28	C/W	Airflow 0 m/s, 4-layer PCB	16
Junction to Case Resistance (Theta JC)	θjc			14.4	C/W	Airflow 0 m/s, 4-layer PCB	16
HIGH Level Input Voltage	VIH	2			V	LVTTL	17
LOW Level Input Voltage	VIL			0.8	V	LVTTL	17
RESET_N LOW to HIGH threshold	VTH+RESET_N	2			V	Schmitt	17
RESET_N HIGH to LOW threshold	VTH-RESET_N			0.8	V	Schmitt	17
DDC Bus LOW to HIGH Threshold	VTH+DDC	3			V	Schmitt	17
DDC Bus HIGH to LOW Threshold	VTH-DDC			1.5	V	Schmitt	17
I2C Bus LOW to HIGH Threshold	VTH+I2C	2			V	Schmitt	17
I2C Bus HIGH to LOW Threshold	VTH-I2C			0.8	V	Schmitt	17
CEC_A LOW to HIGH threshold	VTH+CEC_A	2			V	Schmitt	17
CEC_A HIGH to LOW threshold	VTH-CEC_A			0.8	V	Schmitt	17
DDC LOW Level Output Voltage	VOL_DDC			0.4	V	Open Drain, IOL =, 3 mA	17
I2C LOW Level Output Voltage	VOL_I2C			0.4	V	Open Drain, IOL =, 3 mA	17
Input Leakage Current	IIL	-10		10	µA	LVTTL High Impedance	17
Output Leakage Current	IOL	-10		10	µA	LVTTL High Impedance	17
7.5 mA Digital Output Drive (high)	IOD8	7.5			mA	VOUT = 2.4 V	17
7.5 mA Digital Output Drive (low)	IOD8	7.5			mA	VOUT = 0.4 V	17
CBUS LOW to HIGH threshold	VIH_CBUS	1			V		18
CBUS HIGH to LOW threshold	VIL_CBUS			0.6	V		18
CBUS Output HIGH Voltage	VOH_CBUS	1.5		1.9	V	IO = 100 µA	18
CBUS Output LOW Voltage	VOL_CBUS			0.2	V	IO = 100 µA	18
CBUS HIGH output drive current	IOH_CBUS	2			mA	VOH = 1.5 V	18
CBUS LOW output drive current	IOL_CBUS	300			µA	VOL = 0.2 V	18
CBUS Input Leakage Current	IIL/IIH	-1		1	µA	High impedance	18
CBUS Pull down resistance, discovery	ZCBUS_SINK_DISCOVER	800	1000	1200	Ω		18
CBUS Pull down resistance, ON	ZCBUS_SINK_ON	90	100	110	kΩ		18
HDMI TMDS Differential Mode Input Voltage	VID	150		1200	mV	HDMI mode	18
MHL Differential Mode Input Swing Voltage	VIDF	200		1000	mV	MHL mode	19
HDMI Differential Input Clock Frequency	FRXC	25		165	MHz	HDMI mode	19
MHL Differential Input Clock Frequency	FRXC	25		75	MHz	MHL mode	19
MHL Input Differential Intrapair Skew	TSKEW_DF			93	ps		19
Video Output Rise Time	DLHT			1.5	ns	CL = 10 pF	20
Video Output Fall Time	DHLT			1.5	ns	CL = 10 pF	20
ODCK Frequency	FCIP	25		165	MHz	CL = 10 pF	20
ODCK-to-Output Delay	TCK2OUT	0.4		2.5	ns	CL = 10 pF	20
External Crystal Frequency	FXTAL	26	27	28.5	MHz		21
Speed on Local I2C Port	FI2C			400	kHz	CL = 400 pF	22
RESET_N Signal LOW Time for valid reset	TRESET	2			ms		22
Standby current, 5 V supply (max)	IDDSB		6.3	32	mA	5 V typical; max column as printed	18

CAD (KiCad official)

Symbol: SII9293CNUC
Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
3D model: QFN-72-EP(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: sii9293cnuc-etched.step / sii9293cnuc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sii9293cnuc.step / sii9293cnuc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Lattice datasheet (58 pp, sha256 d4da12913a0624e6, retrieved 2026-10-26, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# SII9293CNUC

**Lattice** · Video Interface ICs · QFN-72-EP(10x10)

SII9293CNUC from Lattice, in a QFN-72-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDH | power_in | Receiver termination 3.3 V analog supply input (3.14-3.46 V), connect to an external 3.3 V regulator or VCC33_OUT. |
| 2 | RXCN | input | TMDS HDMI clock pair negative input. |
| 3 | RXCP | input | TMDS HDMI clock pair positive input. |
| 4 | RX0N | input | TMDS HDMI Channel 0 negative input or MHL input port data pair; other HDMI channels and clock are unused in MHL mode. |
| 5 | RX0P | input | TMDS HDMI Channel 0 positive input or MHL input port data pair; other HDMI channels and clock are unused in MHL mode. |
| 6 | RX1N | input | TMDS HDMI Channel 1 negative input. |
| 7 | RX1P | input | TMDS HDMI Channel 1 positive input. |
| 8 | RX2N | input | TMDS HDMI Channel 2 negative input. |
| 9 | RX2P | input | TMDS HDMI Channel 2 positive input. |
| 10 | VDD | power_in | Digital power, 1.0 V (0.95-1.05 V). |
| 11 | GPIO0_CI2CA | bidirectional | General purpose I/O 0 or CI2CA; defaults to input and is sampled once at reset to select the local I2C address range, LVTTL Schmitt, 5 V tolerant. |
| 12 | GPIO1 | bidirectional | General purpose I/O 1, LVTTL Schmitt, 5 V tolerant. |
| 13 | CSDA | bidirectional | Local I2C data, true open drain, 5 V tolerant, requires external pull-up to 3.3 V. |
| 14 | CSCL | input | Local I2C clock, true open drain, 5 V tolerant, requires external pull-up resistor to 3.3 V. |
| 15 | INT | output | Active-low open-drain interrupt output to host controller, 5 V tolerant, requires external pull-up resistor. |
| 16 | TMODE | output | Test mode enable, open drain, 5 V tolerant; pull down for normal operation. |
| 17 | VCC33_OUT | power_out | Internal 3.3 V regulator output, requires 10 µF capacitor to ground, maximum output current 30 mA. |
| 18 | RESET_N | input | Active-low external reset, Schmitt, 5 V tolerant, internal pull-up; can be left open when not required. |
| 19 | DSDA | bidirectional | DDC I2C data, open drain, 5 V tolerant, carries HDCP KSV, An and Ri; drives low when only SBVCC5V or RPWR5V is present; DDC master for EDID EEPROM in MHL mode. |
| 20 | DSCL | bidirectional | DDC I2C clock, open drain, 5 V tolerant, carries HDCP exchange; drives low when only SBVCC5V or RPWR5V is present; DDC master for EDID EEPROM in MHL mode. |
| 21 | CBUS_HPD | bidirectional | MHL mode: CBUS control signal at 1.8 V level; HDMI mode: HPD output; 5 V tolerant. |
| 22 | RPWR5V | power_in | 5 V port detection input (4.3-5.5 V) from HDMI +5 V or MHL VBUS; needs 10 Ω series resistor, 5.1 kΩ pull-down and at least 1 µF to ground. |
| 23 | SBVCC5V | power_in | Local 5 V power input (4.3-5.5 V), required if no RPWR5V input; needs 10 Ω series resistor. |
| 24 | MHL_CD | input | MHL cable detect input, LVTTL Schmitt, 5 V tolerant. |
| 25 | CBUS_OE | output | LVTTL output enable for CBUS output. |
| 26 | CEC_A | bidirectional | HDMI-compliant CEC I/O, 5 V tolerant, with internal pull-up resistor, connects to the CEC signal of all HDMI connectors. |
| 27 | VDD | power_in | Digital power, 1.0 V (0.95-1.05 V). |
| 28 | GNDIO | power_in | Digital I/O ground. |
| 29 | VDDIO | power_in | Digital I/O power, 3.3 V (3.14-3.46 V). |
| 30 | SD0_SPDIF | output | LVTTL I2S/TDM serial data or S/PDIF audio output. |
| 31 | WS | output | LVTTL I2S word select or TDM frame start (FS) signal. |
| 32 | SCK | output | LVTTL I2S or TDM serial clock. |
| 33 | MCLK | output | LVTTL audio output master clock. |
| 34 | VSYNC | output | LVTTL vertical sync output. |
| 35 | DE | output | LVTTL data enable output. |
| 36 | HSYNC | output | LVTTL horizontal sync output. |
| 37 | Q0 | output | 24-bit output pixel data bus bit 0, LVTTL, configurable format, can be put in high impedance. |
| 38 | Q1 | output | 24-bit output pixel data bus bit 1, LVTTL, configurable format, can be put in high impedance. |
| 39 | Q2 | output | 24-bit output pixel data bus bit 2, LVTTL, configurable format, can be put in high impedance. |
| 40 | Q3 | output | 24-bit output pixel data bus bit 3, LVTTL, configurable format, can be put in high impedance. |
| 41 | Q4 | output | 24-bit output pixel data bus bit 4, LVTTL, configurable format, can be put in high impedance. |
| 42 | Q5 | output | 24-bit output pixel data bus bit 5, LVTTL, configurable format, can be put in high impedance. |
| 43 | Q6 | output | 24-bit output pixel data bus bit 6, LVTTL, configurable format, can be put in high impedance. |
| 44 | Q7 | output | 24-bit output pixel data bus bit 7, LVTTL, configurable format, can be put in high impedance. |
| 45 | GNDIO | power_in | Digital I/O ground. |
| 46 | ODCK | output | LVTTL output data clock. |
| 47 | VDDIO | power_in | Digital I/O power, 3.3 V (3.14-3.46 V). |
| 48 | Q8 | output | 24-bit output pixel data bus bit 8, LVTTL, configurable format, can be put in high impedance. |
| 49 | Q9 | output | 24-bit output pixel data bus bit 9, LVTTL, configurable format, can be put in high impedance. |
| 50 | Q10 | output | 24-bit output pixel data bus bit 10, LVTTL, configurable format, can be put in high impedance. |
| 51 | Q11 | output | 24-bit output pixel data bus bit 11, LVTTL, configurable format, can be put in high impedance. |
| 52 | Q12 | output | 24-bit output pixel data bus bit 12, LVTTL, configurable format, can be put in high impedance. |
| 53 | Q13 | output | 24-bit output pixel data bus bit 13, LVTTL, configurable format, can be put in high impedance. |
| 54 | Q14 | output | 24-bit output pixel data bus bit 14, LVTTL, configurable format, can be put in high impedance. |
| 55 | Q15 | output | 24-bit output pixel data bus bit 15, LVTTL, configurable format, can be put in high impedance. |
| 56 | VDD | power_in | Digital power, 1.0 V (0.95-1.05 V). |
| 57 | Q16 | output | 24-bit output pixel data bus bit 16, LVTTL, configurable format, can be put in high impedance. |
| 58 | Q17 | output | 24-bit output pixel data bus bit 17, LVTTL, configurable format, can be put in high impedance. |
| 59 | Q18 | output | 24-bit output pixel data bus bit 18, LVTTL, configurable format, can be put in high impedance. |
| 60 | Q19 | output | 24-bit output pixel data bus bit 19, LVTTL, configurable format, can be put in high impedance. |
| 61 | GNDIO | power_in | Digital I/O ground. |
| 62 | VDDIO | power_in | Digital I/O power, 3.3 V (3.14-3.46 V). |
| 63 | Q20 | output | 24-bit output pixel data bus bit 20, LVTTL, configurable format, can be put in high impedance. |
| 64 | Q21 | output | 24-bit output pixel data bus bit 21, LVTTL, configurable format, can be put in high impedance. |
| 65 | Q22 | output | 24-bit output pixel data bus bit 22, LVTTL, configurable format, can be put in high impedance. |
| 66 | Q23 | output | 24-bit output pixel data bus bit 23, LVTTL, configurable format, can be put in high impedance. |
| 67 | XTALIN | input | Crystal clock input, LVTTL, 5 V tolerant; can be driven by a clock (XTALOUT unconnected) or connected through a crystal to XTALOUT. |
| 68 | XTALOUT | output | LVTTL crystal clock output. |
| 69 | XTALGND | power_in | Crystal ground. |
| 70 | XTALVCC33 | power_in | Crystal power, 3.3 V (3.14-3.46 V). |
| 71 | APLLVDD | power_in | Analog PLL power, 1.0 V (0.95-1.05 V). |
| 72 | AVDD | power_in | Analog core VDD, 1.0 V (0.95-1.05 V). |
| 73 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Lattice |
| Package | QFN-72-EP(10x10) |
| Category | Interface ICs |
| Pins | 73 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Primary On-chip Regulator Supply Voltage (abs max) | SBVCC5V | -0.3 |  | 5.7 | V |  | 15 |
| Supply Voltage (abs max) | RPWR5V | -0.3 |  | 5.7 | V |  | 15 |
| Digital Core Supply Voltage (abs max) | VDD | -0.3 |  | 1.25 | V |  | 15 |
| Analog Core Supply Voltage (abs max) | AVDD | -0.3 |  | 1.25 | V |  | 15 |
| Analog PLL Supply Voltage (abs max) | APLLVDD | -0.3 |  | 1.25 | V |  | 15 |
| Digital I/O Power Voltage (abs max) | VDDIO | -0.3 |  | 4 | V |  | 15 |
| TMDS I/O Supply Voltage (abs max) | VDDH | -0.3 |  | 4 | V |  | 15 |
| ACR PLL Crystal Oscillator Supply Voltage (abs max) | XTALVCC33 | -0.3 |  | 4 | V |  | 15 |
| Input Voltage (abs max) | VI | -0.3 |  |  | V | max VDDIO + 0.3 V | 15 |
| Output Voltage (abs max) | VO | -0.3 |  |  | V | max VDDIO + 0.3 V | 15 |
| Junction Temperature | TJ |  |  | 125 | C |  | 15 |
| Storage Temperature | TSTG | -65 |  | 150 | C |  | 15 |
| Primary On-chip Regulator Supply Voltage | SBVCC5V | 4.3 | 5 | 5.5 | V |  | 16 |
| Supply Voltage | RPWR5V | 4.3 | 5 | 5.5 | V |  | 16 |
| Digital Core Supply Voltage | VDD | 0.95 | 1 | 1.05 | V |  | 16 |
| Analog Core Supply Voltage | AVDD | 0.95 | 1 | 1.05 | V |  | 16 |
| Analog PLL Supply Voltage | APLLVDD | 0.95 | 1 | 1.05 | V |  | 16 |
| Digital I/O Power Voltage | VDDIO | 3.14 | 3.3 | 3.46 | V |  | 16 |
| TMDS I/O Supply Voltage | VDDH | 3.14 | 3.3 | 3.46 | V |  | 16 |
| ACR PLL Crystal Oscillator Supply Voltage | XTALVCC33 | 3.14 | 3.3 | 3.46 | V |  | 16 |
| 3.3 V Supply Voltage Noise | VDD33N |  |  | 100 | mVP-P |  | 16 |
| Ambient Temperature (with power applied) | TA | -20 | 25 | 85 | C |  | 16 |
| Ambient Thermal Resistance (Theta JA) | θja |  |  | 28 | C/W | Airflow 0 m/s, 4-layer PCB | 16 |
| Junction to Case Resistance (Theta JC) | θjc |  |  | 14.4 | C/W | Airflow 0 m/s, 4-layer PCB | 16 |
| HIGH Level Input Voltage | VIH | 2 |  |  | V | LVTTL | 17 |
| LOW Level Input Voltage | VIL |  |  | 0.8 | V | LVTTL | 17 |
| RESET_N LOW to HIGH threshold | VTH+RESET_N | 2 |  |  | V | Schmitt | 17 |
| RESET_N HIGH to LOW threshold | VTH-RESET_N |  |  | 0.8 | V | Schmitt | 17 |
| DDC Bus LOW to HIGH Threshold | VTH+DDC | 3 |  |  | V | Schmitt | 17 |
| DDC Bus HIGH to LOW Threshold | VTH-DDC |  |  | 1.5 | V | Schmitt | 17 |
| I2C Bus LOW to HIGH Threshold | VTH+I2C | 2 |  |  | V | Schmitt | 17 |
| I2C Bus HIGH to LOW Threshold | VTH-I2C |  |  | 0.8 | V | Schmitt | 17 |
| CEC_A LOW to HIGH threshold | VTH+CEC_A | 2 |  |  | V | Schmitt | 17 |
| CEC_A HIGH to LOW threshold | VTH-CEC_A |  |  | 0.8 | V | Schmitt | 17 |
| DDC LOW Level Output Voltage | VOL_DDC |  |  | 0.4 | V | Open Drain, IOL =, 3 mA | 17 |
| I2C LOW Level Output Voltage | VOL_I2C |  |  | 0.4 | V | Open Drain, IOL =, 3 mA | 17 |
| Input Leakage Current | IIL | -10 |  | 10 | µA | LVTTL High Impedance | 17 |
| Output Leakage Current | IOL | -10 |  | 10 | µA | LVTTL High Impedance | 17 |
| 7.5 mA Digital Output Drive (high) | IOD8 | 7.5 |  |  | mA | VOUT = 2.4 V | 17 |
| 7.5 mA Digital Output Drive (low) | IOD8 | 7.5 |  |  | mA | VOUT = 0.4 V | 17 |
| CBUS LOW to HIGH threshold | VIH_CBUS | 1 |  |  | V |  | 18 |
| CBUS HIGH to LOW threshold | VIL_CBUS |  |  | 0.6 | V |  | 18 |
| CBUS Output HIGH Voltage | VOH_CBUS | 1.5 |  | 1.9 | V | IO = 100 µA | 18 |
| CBUS Output LOW Voltage | VOL_CBUS |  |  | 0.2 | V | IO = 100 µA | 18 |
| CBUS HIGH output drive current | IOH_CBUS | 2 |  |  | mA | VOH = 1.5 V | 18 |
| CBUS LOW output drive current | IOL_CBUS | 300 |  |  | µA | VOL = 0.2 V | 18 |
| CBUS Input Leakage Current | IIL/IIH | -1 |  | 1 | µA | High impedance | 18 |
| CBUS Pull down resistance, discovery | ZCBUS_SINK_DISCOVER | 800 | 1000 | 1200 | Ω |  | 18 |
| CBUS Pull down resistance, ON | ZCBUS_SINK_ON | 90 | 100 | 110 | kΩ |  | 18 |
| HDMI TMDS Differential Mode Input Voltage | VID | 150 |  | 1200 | mV | HDMI mode | 18 |
| MHL Differential Mode Input Swing Voltage | VIDF | 200 |  | 1000 | mV | MHL mode | 19 |
| HDMI Differential Input Clock Frequency | FRXC | 25 |  | 165 | MHz | HDMI mode | 19 |
| MHL Differential Input Clock Frequency | FRXC | 25 |  | 75 | MHz | MHL mode | 19 |
| MHL Input Differential Intrapair Skew | TSKEW_DF |  |  | 93 | ps |  | 19 |
| Video Output Rise Time | DLHT |  |  | 1.5 | ns | CL = 10 pF | 20 |
| Video Output Fall Time | DHLT |  |  | 1.5 | ns | CL = 10 pF | 20 |
| ODCK Frequency | FCIP | 25 |  | 165 | MHz | CL = 10 pF | 20 |
| ODCK-to-Output Delay | TCK2OUT | 0.4 |  | 2.5 | ns | CL = 10 pF | 20 |
| External Crystal Frequency | FXTAL | 26 | 27 | 28.5 | MHz |  | 21 |
| Speed on Local I2C Port | FI2C |  |  | 400 | kHz | CL = 400 pF | 22 |
| RESET_N Signal LOW Time for valid reset | TRESET | 2 |  |  | ms |  | 22 |
| Standby current, 5 V supply (max) | IDDSB |  | 6.3 | 32 | mA | 5 V typical; max column as printed | 18 |

## CAD (KiCad official)

- Symbol: `SII9293CNUC`
- Footprint: `Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm`
- 3D model: QFN-72-EP(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `sii9293cnuc-etched.step` / `sii9293cnuc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sii9293cnuc.step` / `sii9293cnuc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Lattice datasheet](docs/sii9293cnuc-datasheet.pdf) (58 pp, sha256 `d4da12913a0624e6`, retrieved 2026-10-26, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sii9293cnuc-datasheet.pdf)