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SIG7190-ITSP24-RL

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Signal Micro Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SIG7190-ITSP24-RL

Signal Micro · Analog To Digital Converters (ADC) · TSSOP-24

SIG7190-ITSP24-RL from Signal Micro, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLK1 input Crystal connection; used with MCLK2 when CLK[1:0]=00 to run an external crystal (2.5 MHz maximum crystal frequency per the electrical table).
2 MCLK2 bidirectional Master clock input (external clock applied to this pin when CLK[1:0]=01) or internal clock output (when CLK[1:0]=11), depending on MODE register bits CLK[1:0]; tristated when CLK[1:0]=10.
3 SCLK input Serial data clock for the SPI-compatible serial interface.
4 CSn input Serial chip select, active low.
5 P3 output General purpose output bit between AVDD and AGND, enabled by GP32EN in the GPOCON register.
6 P2 output General purpose output bit between AVDD and AGND, enabled by GP32EN in the GPOCON register.
7 P1/REFIN2+ bidirectional General purpose output bit between AVDD and AGND, or second positive reference input (REFIN2+) when used for REFSEL=1.
8 P0/REFIN2- bidirectional General purpose output bit between AVDD and AGND, or second negative reference input (REFIN2-) when used for REFSEL=1.
9 NC unconnected No connection; may float or be connected to AVDD or AGND.
10 AINCOM input Negative analog input for pseudo-differential operation.
11 AIN1 input Analog input channel 1.
12 AIN2 input Analog input channel 2.
13 AIN3 input Analog input channel 3.
14 AIN4 input Analog input channel 4.
15 REFIN1+ input Positive reference input; differential reference VREF = VREFP - VREFN must be between 0.5 V and AVDD - AGND + 0.1 V.
16 REFIN1- input Negative reference input; absolute negative reference voltage must be between AGND - 0.05 V and VREFP - 0.5 V.
17 BPDSW input Bridge power-down switch to AGND, closed under control of the GPOCON BPDSW bit (typical on-resistance 3 Ohms).
18 AGND power_in Negative analog power supply; may be taken below DGND to provide bipolar supplies (e.g. AGND = -2.5 V with AVDD = +2.5 V), with the AGND voltage limited to -2.625 V to 0 V.
19 DGND power_in Digital ground reference point.
20 AVDD power_in Positive analog power supply, 2.7 V to 5.25 V relative to AGND, independent of DVDD.
21 DVDD power_in Digital power supply, 2.7 V to 5.25 V, independent of AVDD.
22 SYNCn_PDn input Synchronization control: while low, the digital filter is reset and DOUT is forced high; holding low for longer than 0.83 ms powers the device down.
23 DOUT/DRDYn output Serial data output and data-ready indicator; goes low when new conversion data is available.
24 DIN input Serial data input.

Key specifications

Parameter Value
Manufacturer Signal Micro
Package TSSOP-24
Category Data Acquisition
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AGND voltage -0.3 6.5 V 3
AGND to DGND voltage -3 0.3 V 3
DVDD to DGND voltage -0.3 6.5 V 3
Current input current -10 10 mA 3
Junction temperature (TJ) TJ -50 150 °C 3
Storage temperature (Tstg) Tstg -60 150 °C 3
ESD HBM, human-body model HBM -8000 8000 V ANSI/ESDA/JEDEC JS-001 3
ESD CDM, charged-device model CDM -2000 2000 V JEDEC EIA/JESD22-C101F 3
ESD MM, machine model MM -600 600 V JEDEC EIA/JESD22-A115C 3
Specified temperature range -40 125 °C 5
Operating temperature range -50 125 °C 5
AGND voltage VAGND -2.625 0 V 5
DVDD voltage VDVDD 2.7 5.25 V 5
Absolute input current -100 100 nA Buffer off, Gain=1 4
Absolute input current -2 2 nA Buffer On 4
Data rate 4.7 4800 SPS 4
Integral nonlinearity (INL) -10 10 ppm Buffer Off, Gain=1 4
Integral nonlinearity (INL) -2 2 ppm Buffer On 4
Offset drift vs. temperature -2 2 nV/°C All PGA gains; printed as ±150/Gain ± 2 nV/°C, the ±2 value is used 4
Gain error -200 ppm Gain = 1, 2, and 4; min/max at +25°C only (note 2) 4
Gain error -250 ppm Gain = 8, 16, and 32; min/max at +25°C only (note 2) 4
Gain error -350 ppm Gain = 64 and 128; min/max at +25°C only (note 2) 4
Gain mismatch 150 350 ppm All PGA gains; min/max at +25°C only (note 2) 4
Gain drift vs. temperature -3 3 ppm/°C All PGA gains 4
Common mode rejection (CMRR) CMRR 100 120 dB fIN = 50Hz, data rate = 1200SPS 4
Power supply rejection AVDD, AGND (PSRR) PSRR 85 105 dB AVDD, AGND 4
Power supply rejection DVDD (PSRR) PSRR 90 110 dB DVDD 4
Differential reference voltage VREF 0.5 V VREF = VREFP, VREFN; printed maximum is a formula (VAVDD, VAGND + 0.1), not computed 4
Average voltage input current -500 500 nA 4
External clock frequency range 1 4.9152 5 MHz 4
External clock duty cycle 40 60 % 4
Internal oscillator accuracy -3 3 % Printed as -3% ±0.5% 3%; typ ±0.5 not used 4
Crystal oscillation frequency range 1 4.9152 2.5 MHz As printed (printed max 2.5 is below printed typ) 4
Input leakage (digital input) -10 10 μA 5
AVDD, AGND current (IAVDD) IAVDD 0.9 1.3 mA Buffer Off 5
AVDD, AGND current (IAVDD) IAVDD 2.5 3.2 mA Buffer On 5
DVDD current (IDVDD) IDVDD 260 360 μA Active Mode 5
t1 CSn falling edge to DOUT/DRDYn driven (propagation delay) t1 50 ns DOUT load = 20pF // 100kΩ to DGND 6
t2 SCLK falling edge to valid DOUT/DRDYn (propagation delay) t2 50 ns DOUT load = 20pF // 100kΩ to DGND 6
SCLK low pulse width t3 100 ns 6
SCLK high pulse width t4 100 ns 6
SCLK period 200 ns Printed max value '106' is ambiguous and omitted 6
CSn rising edge to DOUT high impedance (propagation delay) t5 40 ns 6
Last SCLK rising edge to CSn rising edge (delay time) t6 50 ns 6
CSn high pulse width t7 50 ns 6
CSn falling edge to first SCLK falling edge (setup time) t8 50 ns CSn can be tied low 6
Valid DIN to SCLK rising edge (setup time) t9 50 ns 6
Valid DIN to SCLK rising edge (hold time) t10 25 ns 6

CAD (KiCad official)

  • Symbol: SIG7190-ITSP24-RL
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: sig7190-itsp24-rl-etched.step / sig7190-itsp24-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sig7190-itsp24-rl.step / sig7190-itsp24-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Signal Micro datasheet (16 pp, sha256 18c49f968cf7faff, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF