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SIG5530A-ITSP20-RL

Public Made by Adom

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Signal Micro Analog To Digital Converters (ADC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SIG5530A-ITSP20-RL

Signal Micro · Analog To Digital Converters (ADC) · TSSOP-20

SIG5530A-ITSP20-RL from Signal Micro, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN1+ input Positive analog input channel 1.
2 AIN1- input Negative analog input channel 1.
3 C1 output Amplifier analog output; connect a C0G capacitor of 4.7~22nF between C1 and C2.
4 C2 output Amplifier analog output; connect a C0G capacitor of 4.7~22nF between C1 and C2.
5 AVDD power_in Positive analog power supply, 4.75V to 5.25V relative to AVSS.
6 AVSS power_in Negative analog power supply (VAVSS specified from -2.625V to 0V).
7 A0/PDSW output Analog logic output or bridge power-down switch.
8 A1 output Analog logic output.
9 OSC2 bidirectional Master clock input or crystal connection.
10 OSC1 input Crystal connection.
11 SCLK input Serial data clock.
12 DOUT/DRDYn output Serial data output and data ready indicator.
13 DIN input Serial data input.
14 CSn input Serial chip select, active low.
15 DVDD power_in Digital power supply, 2.7V to 5.25V, independent of AVDD.
16 DGND power_in Digital ground reference point.
17 REF- input Negative reference input.
18 REF+ input Positive reference input.
19 AIN2- input Negative analog input channel 2.
20 AIN2+ input Positive analog input channel 2.

Key specifications

Parameter Value
Manufacturer Signal Micro
Package TSSOP-20
Category Data Acquisition
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS -0.3 6.5 V 3
AVSS to DGND -3 0.3 V 3
DVDD to DGND -0.3 6.5 V 3
Input current -10 10 mA 3
Junction temperature TJ -50 150 °C 3
Storage temperature Tstg -60 150 °C 3
ESD HBM HBM -4000 4000 V ANSI/ESDA/JEDEC JS-001 3
ESD CDM CDM -2000 2000 V JEDEC EIA/JS-002-2022 3
Absolute Input Current -2 2 nA 4
Data Rate SIG5530A 1.875 1920 SPS 4
Integral Nonlinearity INL -3 3 ppm 4
Offset Error -3 3 μV 4
Offset Drift vs. Temperature -5 5 nV/°C 4
Gain Error -0.3 0.3 % +25°C only 4
Gain Drift vs. Temperature -3 0.5 3 ppm/°C 4
Common Mode Rejection CMRR 100 120 dB fIN=50/60Hz, data rate=960SPS 4
Power Supply Rejection AVDD, AVSS PSRR 75 90 dB AVDD, AVSS 4
Power Supply Rejection DVDD PSRR 80 120 dB DVDD 4
Differential Reference Voltage VREF 0.5 0 V VREF = VREFP, VREFN; max printed as VAVDD, VAVSS + 0.1 4
External Clock Frequency Range 1 4.9152 5 MHz 4
Duty Cycle 40 60 % 4
Internal Oscillator Accuracy -3 0.5 3 % typ printed ±0.5% 4
Input Hysteresis 0.5 V 4
Input Leakage -10 10 μA 4
AVSS Voltage VAVSS -2.625 0 V 4
DVDD Voltage VDVDD 2.7 5.25 V 4
AVDD, AVSS Current Active Mode IAVDD 3.6 4.5 mA Active Mode 4
DVDD Current Active Mode IDVDD 0.4 0.6 mA Active Mode 5
Specified temperature range -40 125 °C 5
Operating temperature range -50 125 °C 5
Storage temperature range -60 150 °C 5
CSn falling edge to valid DOUT/DRDYn delay t1 20 ns DOUT load = 20pF // 100k Ω to DGND 6
SCLK falling edge to valid DOUT/DRDYn delay t2 20 ns DOUT load = 20pF // 100k Ω to DGND 6
SCLK high pulse width t3 50 ns 6
SCLK low pulse width t4 50 ns 6
SCLK period 100 106 ns 6
CSn rising edge to DOUT high impedance delay t5 20 ns 6
Last SCLK falling edge to CSn rising edge delay t6 20 ns 6
CSn high pulse width t7 50 ns 6
CSn falling edge to first SCLK rising edge setup t8 50 ns CSn can be tied low 6
Valid DIN to SCLK rising edge setup t9 20 ns 6
Valid DIN to SCLK rising edge hold t10 20 ns 6

CAD (KiCad official)

  • Symbol: SIG5530A-ITSP20-RL
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sig5530a-itsp20-rl-etched.step / sig5530a-itsp20-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sig5530a-itsp20-rl.step / sig5530a-itsp20-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Signal Micro datasheet (14 pp, sha256 21b27c3ec576f399, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF