component

SI9634DY-T1-GE3

Public Made by Adom

by adom

Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorssi9634dy-t1-ge3factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers si9634dy-t1-ge3: viewers · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3-etched.glb Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3-etched.step si9634dy-t1-ge3: factory component page (tier=mfr) · Ray 10d ago
si9634dy-t1-ge3-hero.glb si9634dy-t1-ge3: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
si9634dy-t1-ge3-hero.overlay.json Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3.glb Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3.kicad_mod Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3.kicad_sym Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3.lbr Publish 0.1.0 · Ray 10d ago
si9634dy-t1-ge3.step Publish 0.1.0 · Ray 10d ago

SI9634DY-T1-GE3

Vishay Intertech · MOSFETs · SO-8

SI9634DY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of N-channel MOSFET 1 (dual 60 V, 8 A TrenchFET device); the datasheet gives VDS 60 V and VGS ±20 V as absolute maximum ratings.
2 G1 input Gate of N-channel MOSFET 1; gate-source voltage is limited to ±20 V per the absolute maximum ratings.
3 S2 passive Source terminal of N-channel MOSFET 2 (dual 60 V, 8 A TrenchFET device); the datasheet gives VDS 60 V and VGS ±20 V as absolute maximum ratings.
4 G2 input Gate of N-channel MOSFET 2; gate-source voltage is limited to ±20 V per the absolute maximum ratings.
5 D2 passive Drain terminal of N-channel MOSFET 2, rated for 60 V drain-source voltage per the absolute maximum ratings.
6 D2 passive Drain terminal of N-channel MOSFET 2, rated for 60 V drain-source voltage per the absolute maximum ratings.
7 D1 passive Drain terminal of N-channel MOSFET 1, rated for 60 V drain-source voltage per the absolute maximum ratings.
8 D1 passive Drain terminal of N-channel MOSFET 1, rated for 60 V drain-source voltage per the absolute maximum ratings.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS 60 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID 8 A TJ = 150 °C; TC = 25 °C; note a 1
Continuous drain current ID 6.6 A TJ = 150 °C; TC = 70 °C 1
Continuous drain current ID 6.2 A TJ = 150 °C; TA = 25 °C; notes b, c 1
Continuous drain current ID 5 A TJ = 150 °C; TA = 70 °C; notes b, c 1
Pulsed drain current IDM 32 A t = 100 μs 1
Continuous source-drain diode current IS 3 A TC = 25 °C 1
Continuous source-drain diode current IS 1.7 A TA = 25 °C; notes b, c 1
Single pulse avalanche current IAS 10 A L = 0.1 mH 1
Single pulse avalanche energy EAS 5 mJ 1
Maximum power dissipation PD 3.6 W TC = 25 °C 1
Maximum power dissipation PD 2.3 W TC = 70 °C 1
Maximum power dissipation PD 2 W TA = 25 °C; notes b, c 1
Maximum power dissipation PD 1.3 W TA = 70 °C; notes b, c 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Soldering recommendations (peak temperature) 260 °C note c 1
Maximum junction-to-ambient RthJA 50 62.5 °C/W t = 10 s; notes b, e 1
Maximum junction-to-foot (drain) RthJF 28 35 °C/W Steady state 1
Drain-source breakdown voltage VDS 60 V VGS = 0 V, ID = 250 μA 2
Gate-source threshold voltage VGS(th) 1 3 V VDS = VGS, ID = 250 μA 2
Gate-source leakage IGSS 100 nA VDS = 0 V, VGS = ±20 2
Zero gate voltage drain current IDSS 1 μA VDS = 60 V, VGS = 0 V 2
Zero gate voltage drain current IDSS 15 μA VDS = 60 V, VGS = 0 V, TJ = 70 °C 2
Drain-source on-state resistance RDS(on) 0.022 0.029 Ω VGS = 10 V, ID = 5 A 2
Drain-source on-state resistance RDS(on) 0.029 0.038 Ω VGS = 4.5 V, ID = 4 A 2
Total gate charge Qg 7.1 11 nC VDS = 30 V, VGS = 10 V, ID = 5 A 2
Total gate charge Qg 3.3 5 nC VDS = 30 V, VGS = 4.5 V, ID = 5 A 2
Gate resistance Rg 0.3 1.6 3.2 Ω f = 1 MHz 2
Turn-on delay time td(on) 10 20 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 10 V, Rg = 1 2
Rise time tr 5 10 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 10 V, Rg = 1 2
Turn-off delay time td(off) 15 30 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 10 V, Rg = 1 2
Fall time tf 5 10 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 10 V, Rg = 1 2
Turn-on delay time td(on) 12 25 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 4.5 V, Rg = 1 2
Rise time tr 16 35 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 4.5 V, Rg = 1 2
Turn-off delay time td(off) 11 25 ns VDD = 30 V, RL = 6, ID 5 A, VGEN = 4.5 V, Rg = 1 2
Continuous source-drain diode current IS 8 A TC = 25 °C 2
Pulse diode forward current ISM 32 A 2
Body diode voltage VSD 0.8 1.2 V IS = 2 A, VGS = 0 V 2
Body diode reverse recovery time trr 14 30 ns IF = 5 A, dI/dt = 100 A/μs, TJ = 25 °C 2
Body diode reverse recovery charge Qrr 10 20 nC IF = 5 A, dI/dt = 100 A/μs, TJ = 25 °C 2

CAD (KiCad official)

  • Symbol: SI9634DY-T1-GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si9634dy-t1-ge3-etched.step / si9634dy-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si9634dy-t1-ge3.step / si9634dy-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (7 pp, sha256 88b04877f3e64ef9, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF