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SI8662BC-B-IS1

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SILICON LABS Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icssi8662bc-b-is1factory-2.0.0extractor-text

Verified SI8662BC-B-IS1

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SI8662BC-B-IS1 · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 42-page datasheet
  • ✓distributor: lcsc C430288, digikey 336-2124-5-ND, mouser 634-SI8662BC-B-IS1
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qso7zwoh/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.32)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ si8662bc-b-is1.kicad_sym✓ si8662bc-b-is1.kicad_mod✓ si8662bc-b-is1.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers si8662bc-b-is1: viewers · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1-etched.glb Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1-etched.step si8662bc-b-is1: factory component page (tier=lcsc) · Ray 10d ago
si8662bc-b-is1-hero.glb si8662bc-b-is1: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
si8662bc-b-is1-hero.overlay.json Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1.glb Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1.kicad_mod Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1.kicad_sym Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1.lbr Publish 0.1.0 · Ray 10d ago
si8662bc-b-is1.step Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray 10d ago

SI8662BC-B-IS1

SILICON LABS · Digital Isolators · SOIC-16

SI8662BC-B-IS1 from SILICON LABS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply; the device requires a 0.1 µF bypass capacitor between VDD1 and GND1 placed as close to the package as possible.
2 A1 input Side 1 digital input.
3 A2 input Side 1 digital input.
4 A3 input Side 1 digital input.
5 A4 bidirectional Side 1 digital input or output.
6 A5 bidirectional Side 1 digital input or output.
7 A6 bidirectional Side 1 digital input or output.
8 GND1 power_in Side 1 ground.
9 GND2 power_in Side 2 ground.
10 B6 bidirectional Side 2 digital input or output.
11 B5 bidirectional Side 2 digital input or output.
12 B4 bidirectional Side 2 digital input or output.
13 B3 output Side 2 digital output.
14 B2 output Side 2 digital output.
15 B1 output Side 2 digital output.
16 VDD2 power_in Side 2 power supply.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Junction Operating Temperature TJ 150 °C 11
Ambient Operating Temperature TA -40 25 125 °C 11
Supply Voltage VDD1 VDD1 2.375 5.5 V 11
Supply Voltage VDD2 VDD2 2.375 5.5 V 11
Storage Temperature TSTG -65 150 °C 26
Ambient Temperature Under Bias TA -40 125 °C 26
Junction Temperature TJ 150 °C 26
Supply Voltage VDD1, VDD2 -0.5 7 V 26
Input Voltage VI -0.5 V Maximum printed as VDD + 0.5 26
Output Voltage VO -0.5 V Maximum printed as VDD + 0.5 26
Output Current Drive Channel IO 10 mA 26
Lead Solder Temperature 260 °C 10 s 26
Maximum Isolation (Input to Output) 4500 VRMS 1 sec; NB SOIC-16, QSOP-16 26
IC Junction-to-Air Thermal Resistance θJA 105 °C/W NB SOIC-16/QSOP-16 package 24
VDD Undervoltage Threshold (rising) VDDUV+ 1.95 2.24 2.375 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C; VDD1, VDD2 rising 11
VDD Undervoltage Threshold (falling) VDDUV- 1.88 2.16 2.325 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C; VDD1, VDD2 falling 11
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C; All inputs rising 11
Negative-Going Input Threshold VT- 1 1.23 1.4 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C; All inputs falling 11
Input Hysteresis VHYS 0.38 0.44 0.5 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
High Level Input Voltage VIH 2 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
Low Level Input Voltage VIL 0.8 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
High Level Output Voltage (5 V) VOH 4.8 V loh = -4 mA; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
Low Level Output Voltage VOL 0.2 0.4 V lol = 4 mA; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
Input Leakage Current IL -10 10 µA VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 11
DC Supply Current, VDD1 (VI = 0(Bx)) 2.2 3.3 mA All inputs 0 V or at supply; VI = 0(Bx), 1(Ex); VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
DC Supply Current, VDD2 (VI = 0(Bx)) 3 4.5 mA All inputs 0 V or at supply; VI = 0(Bx), 1(Ex); VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
DC Supply Current, VDD1 (VI = 1(Bx)) 7.5 10.5 mA All inputs 0 V or at supply; VI = 1(Bx), 0(Ex); VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
DC Supply Current, VDD2 (VI = 1(Bx)) 5.6 8.4 mA All inputs 0 V or at supply; VI = 1(Bx), 0(Ex); VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
1 Mbps Supply Current, VDD1 5.1 7.1 mA All inputs = 500 kHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
1 Mbps Supply Current, VDD2 4.7 6.6 mA All inputs = 500 kHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
10 Mbps Supply Current, VDD1 (5 V) 5.6 7.9 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
10 Mbps Supply Current, VDD2 (5 V) 5.9 8.2 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
100 Mbps Supply Current, VDD1 (5 V) 12.8 16.6 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
100 Mbps Supply Current, VDD2 (5 V) 19.4 25.2 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Maximum Data Rate 0 150 Mbps VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Minimum Pulse Width 5 ns VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Propagation Delay (5 V) tPHL, tPLH 5 8 13 ns See Figure 4.1; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Pulse Width Distortion (5 V) PWD 0.2 4.5 ns See Figure 4.1; /tPLH − tPHL/; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Propagation Delay Skew (5 V) tPSK(P-P) 2 4.5 ns VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Channel-Channel Skew tPSK 0.4 2.5 ns VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Output Rise Time tr 2.5 4 ns CL = 15 pF; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Output Fall Time tf 2.5 4 ns CL = 15 pF; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 13
Common Mode Transient Immunity CMTI 35 50 kV/µs VI = VDD or 0 V; VCM = 1500 V; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 14
Startup Time tSU 15 40 µs VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 14
10 Mbps Supply Current, VDD1 (3.3 V) 5.3 7.4 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = -40 to 125 °C 17
10 Mbps Supply Current, VDD2 (3.3 V) 5.2 7.3 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = -40 to 125 °C 17
100 Mbps Supply Current, VDD1 (3.3 V) 10 13 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = -40 to 125 °C 17
100 Mbps Supply Current, VDD2 (3.3 V) 14.1 18.3 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = -40 to 125 °C 17
High Level Output Voltage (3.3 V) VOH 3.1 V loh = -4 mA; VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = -40 to 125 °C 15
High Level Output Voltage (2.5 V) VOH 2.3 V loh = -4 mA; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 19
10 Mbps Supply Current, VDD1 (2.5 V) 5.2 7.2 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 20
10 Mbps Supply Current, VDD2 (2.5 V) 4.9 6.9 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 20
100 Mbps Supply Current, VDD1 (2.5 V) 8.7 11.3 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 21
100 Mbps Supply Current, VDD2 (2.5 V) 11.7 15.2 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 21
Propagation Delay (2.5 V) tPHL, tPLH 5 8 14 ns See Figure 4.1; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 21
Pulse Width Distortion (2.5 V) PWD 0.2 5 ns See Figure 4.1; /tPLH − tPHL/; VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 21
Propagation Delay Skew (2.5 V) tPSK(P-P) 2 5 ns VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = -40 to 125 °C 21

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Package Outline (16-Pin Wide Body SOIC) silabs.com / Building a more connected world. Rev. 1.73 / 28 28

CAD (KiCad official)

  • Symbol: SI8662BC-B-IS1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: si8662bc-b-is1-etched.step / si8662bc-b-is1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8662bc-b-is1.step / si8662bc-b-is1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (42 pp, sha256 359b0b0d642bba99, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF