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verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 10h ago

SI8661BB-B-IUR

Skyworks Solutions · Digital Isolators · QSOP-16

SI8661BB-B-IUR from Skyworks Solutions, in a QSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, operating range 2.375 to 5.5 V, with a 0.1 µF bypass capacitor to GND1 placed close to the package.
2 A1 input Side 1 digital input.
3 A2 input Side 1 digital input.
4 A3 input Side 1 digital input.
5 A4 input Side 1 digital input (A4 is an input on the Si8661).
6 A5 input Side 1 digital input (A5 is an input on the Si8661).
7 A6 output Side 1 digital output in the Si8661, driven from the side 2 input B6 (the pin is listed as digital input or output).
8 GND1 power_in Side 1 ground.
9 GND2 power_in Side 2 ground.
10 B6 input Side 2 digital input in the Si8661, driving output A6 (the pin is listed as digital input or output).
11 B5 output Side 2 digital output (B5 is an output on the Si8661).
12 B4 output Side 2 digital output (B4 is an output on the Si8661).
13 B3 output Side 2 digital output.
14 B2 output Side 2 digital output.
15 B1 output Side 2 digital output.
16 VDD2 power_in Side 2 power supply, operating range 2.375 to 5.5 V, with a 0.1 µF bypass capacitor to GND2 placed close to the package.

Key specifications

Parameter Value
Manufacturer Skyworks Solutions
Package QSOP-16
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Junction Operating Temperature TJ 150 °C 11
Ambient Operating Temperature TA -40 25 125 °C 11
Supply Voltage VDD1 VDD1 2.375 5.5 V 11
Supply Voltage VDD2 VDD2 2.375 5.5 V 11
Storage Temperature TSTG -65 150 °C 26
Ambient Temperature Under Bias TA -40 125 °C 26
Junction Temperature TJ 150 °C 26
Supply Voltage VDD1, VDD2 -0.5 7 V 26
Input Voltage VI -0.5 V 26
Output Voltage VO -0.5 V 26
Output Current Drive Channel IO 10 mA 26
Lead Solder Temperature 260 °C 10 s 26
Maximum Isolation (Input to Output), NB SOIC-16, QSOP-16 4500 VRMS 1 sec 26
IC Junction-to-Air Thermal Resistance θJA 105 °C/W NB SOIC-16/QSOP-16 package 24
VDD Undervoltage Threshold VDDUV+ VDDUV+ 1.95 2.24 2.375 V 5 V ±10%; VDD1, VDD2 rising 11
VDD Undervoltage Threshold VDDUV- VDDUV- 1.88 2.16 2.325 V 5 V ±10%; VDD1, VDD2 falling 11
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 5 V ±10% 11
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V 5 V ±10%; All inputs rising 11
Negative-Going Input Threshold VT- 1 1.23 1.4 V 5 V ±10%; All inputs falling 11
Input Hysteresis VHYS 0.38 0.44 0.5 V 5 V ±10% 11
High Level Input Voltage VIH 2 V 5 V ±10% 11
Low Level Input Voltage VIL 0.8 V 5 V ±10% 11
High Level Output Voltage VOH 4.8 V 5 V ±10%; loh = -4 mA 11
Low Level Output Voltage VOL 0.2 0.4 V 5 V ±10%; lol = 4 mA 11
Input Leakage Current IL -10 10 µA 5 V ±10% 11
DC Supply Current VDD1 1.7 2.7 mA 5 V ±10%; VI = 0(Bx) 12
DC Supply Current VDD2 3.4 5.1 mA 5 V ±10%; VI = 0(Bx) 12
DC Supply Current VDD1 7.9 11.1 mA 5 V ±10%; VI = 1(Bx) 12
DC Supply Current VDD2 4.8 7.2 mA 5 V ±10%; VI = 1(Bx) 12
1 Mbps Supply Current VDD1 4.9 6.9 mA 5 V ±10%; All inputs = 500 kHz square wave, CI = 15 pF 12
1 Mbps Supply Current VDD2 4.6 6.4 mA 5 V ±10%; All inputs = 500 kHz square wave, CI = 15 pF 12
10 Mbps Supply Current VDD1 5.2 7.3 mA 5 V ±10%; All inputs = 5 MHz square wave, CI = 15 pF 12
10 Mbps Supply Current VDD2 6.1 8.5 mA 5 V ±10%; All inputs = 5 MHz square wave, CI = 15 pF 12
100 Mbps Supply Current VDD1 8.8 11.8 mA 5 V ±10%; All inputs = 50 MHz square wave, CI = 15 pF 13
100 Mbps Supply Current VDD2 23 29.8 mA 5 V ±10%; All inputs = 50 MHz square wave, CI = 15 pF 13
Maximum Data Rate 0 150 Mbps 5 V ±10% 13
Minimum Pulse Width 5 ns 5 V ±10% 13
Propagation Delay tPHL, tPLH tPHL, tPLH 5 8 13 ns 5 V ±10%; see Figure 4.1 13
Pulse Width Distortion /tPLH - tPHL/ PWD 0.2 4.5 ns 5 V ±10%; see Figure 4.1 13
Propagation Delay Skew tPSK(P-P) 2 4.5 ns 5 V ±10% 13
Channel-Channel Skew tPSK 0.4 2.5 ns 5 V ±10% 13
Output Rise Time tr 2.5 4 ns 5 V ±10%; CL = 15 pF 13
Output Fall Time tf 2.5 4 ns 5 V ±10%; CL = 15 pF 13
Common Mode Transient Immunity CMTI 35 50 kV/µs 5 V ±10%; VI = VDD or 0 V, VCM = 1500 V 14
Startup Time tSU 15 40 µs 5 V ±10% 14
High Level Output Voltage VOH 3.1 V 3.3 V ±10%; loh = -4 mA 15
10 Mbps Supply Current VDD1 5 7 mA 3.3 V ±10%; All inputs = 5 MHz square wave, CI = 15 pF 17
10 Mbps Supply Current VDD2 5.3 7.4 mA 3.3 V ±10%; All inputs = 5 MHz square wave, CI = 15 pF 17
100 Mbps Supply Current VDD1 7.4 9.9 mA 3.3 V ±10%; All inputs = 50 MHz square wave, CI = 15 pF 17
100 Mbps Supply Current VDD2 16.4 21.3 mA 3.3 V ±10%; All inputs = 50 MHz square wave, CI = 15 pF 17
High Level Output Voltage VOH 2.3 V 2.5 V ±5%; loh = -4 mA 19
10 Mbps Supply Current VDD1 5 6.9 mA 2.5 V ±5%; All inputs = 5 MHz square wave, CI = 15 pF 20
10 Mbps Supply Current VDD2 4.9 6.9 mA 2.5 V ±5%; All inputs = 5 MHz square wave, CI = 15 pF 20
100 Mbps Supply Current VDD1 6.7 9.1 mA 2.5 V ±5%; All inputs = 50 MHz square wave, CI = 15 pF 21
100 Mbps Supply Current VDD2 13.4 17.4 mA 2.5 V ±5%; All inputs = 50 MHz square wave, CI = 15 pF 21
Propagation Delay tPHL, tPLH tPHL, tPLH 5 8 14 ns 2.5 V ±5%; see Figure 4.1 21
Pulse Width Distortion /tPLH - tPHL/ PWD 0.2 5 ns 2.5 V ±5%; see Figure 4.1 21
Propagation Delay Skew tPSK(P-P) 2 5 ns 2.5 V ±5% 21

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32

CAD (KiCad official)

  • Symbol: SI8661BB-B-IUR
  • Footprint: Package_SO:QSOP-16_3.9x4.9mm_P0.635mm
  • 3D model: QSOP-16 (KiCad packages3D, STEP)
  • 3D model files: si8661bb-b-iur-etched.step / si8661bb-b-iur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8661bb-b-iur.step / si8661bb-b-iur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Skyworks Solutions datasheet (42 pp, sha256 aea8c0805c804419, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF