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SI8660BD-B-ISR

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SILICON LABS Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI8660BD-B-ISR

SILICON LABS · Digital Isolators · SOIC-16-300mil

SI8660BD-B-ISR from SILICON LABS, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, operated between 2.5 V and 5.5 V and requiring a 0.1 µF bypass capacitor to GND1 placed as close to the package as possible.
2 A1 input Side 1 digital input with Schmitt trigger input for high noise immunity.
3 A2 input Side 1 digital input with Schmitt trigger input for high noise immunity.
4 A3 input Side 1 digital input with Schmitt trigger input for high noise immunity.
5 A4 bidirectional Side 1 digital input or output; the output has a nominal impedance of approximately 50 Ω ±40%.
6 A5 bidirectional Side 1 digital input or output; the output has a nominal impedance of approximately 50 Ω ±40%.
7 A6 bidirectional Side 1 digital input or output; the output has a nominal impedance of approximately 50 Ω ±40%.
8 GND1 power_in Side 1 ground, the reference for VDD1 and the Side 1 inputs and outputs.
9 GND2 power_in Side 2 ground, the reference for VDD2 and the Side 2 inputs and outputs.
10 B6 bidirectional Side 2 digital input or output; the output has a nominal impedance of approximately 50 Ω ±40%.
11 B5 bidirectional Side 2 digital input or output; the output has a nominal impedance of approximately 50 Ω ±40%.
12 B4 bidirectional Side 2 digital input or output; the output has a nominal impedance of approximately 50 Ω ±40%.
13 B3 output Side 2 digital output; the output has a nominal impedance of approximately 50 Ω ±40%.
14 B2 output Side 2 digital output; the output has a nominal impedance of approximately 50 Ω ±40%.
15 B1 output Side 2 digital output; the output has a nominal impedance of approximately 50 Ω ±40%.
16 VDD2 power_in Side 2 power supply, operated between 2.5 V and 5.5 V and requiring a 0.1 µF bypass capacitor to GND2 placed as close to the package as possible.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Junction Operating Temperature TJ 150 °C 11
Ambient Operating Temperature TA -40 25 125 °C Max depends on data frequency, output loading, channel count, supply (note 1) 11
Supply Voltage VDD1 VDD1 2.375 5.5 V 11
Supply Voltage VDD2 VDD2 2.375 5.5 V 11
Storage Temperature TSTG -65 150 °C Note 2: VDE certifies -40 to 150 °C 26
Ambient Temperature Under Bias TA -40 125 °C 26
Junction Temperature TJ 150 °C 26
Supply Voltage VDD1, VDD2 -0.5 7 V 26
Input Voltage VI -0.5 V Printed max is VDD + 0.5 V (formula) 26
Output Voltage VO -0.5 V Printed max is VDD + 0.5 V (formula) 26
Output Current Drive Channel IO 10 mA 26
Lead Solder Temperature 260 °C 10 s 26
Maximum Isolation (Input to Output) 6500 VRMS 1 s; WB SOIC-16 package 26
VDD Undervoltage Threshold rising VDDUV+ 1.95 2.24 2.375 V VDD 5 V ±10%: VDD1, VDD2 rising 11
VDD Undervoltage Threshold falling VDDUV- 1.88 2.16 2.325 V VDD 5 V ±10%: VDD1, VDD2 falling 11
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV VDD 5 V ±10% 11
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V VDD 5 V ±10%: All inputs rising 11
Negative-Going Input Threshold VT- 1 1.23 1.4 V VDD 5 V ±10%: All inputs falling 11
Input Hysteresis VHYS 0.38 0.44 0.5 V VDD 5 V ±10% 11
High Level Input Voltage VIH 2 V VDD 5 V ±10% 11
Low Level Input Voltage VIL 0.8 V VDD 5 V ±10% 11
Low Level Output Voltage VOL 0.2 0.4 V VDD 5 V ±10%: lol = 4 mA 11
Input Leakage Current IL -10 10 µA VDD 5 V ±10% 11
Output Impedance tolerance ZO -40 40 % Nominal 50 Ω (Table 4.2 note 1) 11
DC Supply Current VDD1 (Si8660Bx, VI = 0) 1.2 1.9 mA VDD 5 V ±10%: All inputs 0 V or at supply; VI = 0(Bx), 1(Ex) 11
DC Supply Current VDD2 (Si8660Bx, VI = 0) 3.5 5.3 mA VDD 5 V ±10%: All inputs 0 V or at supply; VI = 0(Bx), 1(Ex) 11
DC Supply Current VDD1 (Si8660Bx, VI = 1) 8.8 12.3 mA VDD 5 V ±10%: All inputs 0 V or at supply; VI = 1(Bx), 0(Ex) 11
DC Supply Current VDD2 (Si8660Bx, VI = 1) 3.7 5.6 mA VDD 5 V ±10%: All inputs 0 V or at supply; VI = 1(Bx), 0(Ex) 11
1 Mbps Supply Current VDD1 5 7 mA VDD 5 V ±10%: All inputs 500 kHz square wave, CI = 15 pF 12
1 Mbps Supply Current VDD2 4.2 5.9 mA VDD 5 V ±10%: All inputs 500 kHz square wave, CI = 15 pF 12
10 Mbps Supply Current VDD1 5 7 mA VDD 5 V ±10%: All inputs 5 MHz square wave, CI = 15 pF 12
10 Mbps Supply Current VDD2 5.9 8.3 mA VDD 5 V ±10%: All inputs 5 MHz square wave, CI = 15 pF 12
100 Mbps Supply Current VDD1 5 7 mA VDD 5 V ±10%: All inputs 50 MHz square wave, CI = 15 pF 13
100 Mbps Supply Current VDD2 26.2 34.1 mA VDD 5 V ±10%: All inputs 50 MHz square wave, CI = 15 pF 13
Maximum Data Rate 0 150 Mbps Si866xBx, Ex 13
Minimum Pulse Width 5 ns 13
Propagation Delay tPHL, tPLH 5 8 13 ns VDD 5 V ±10%: See Figure 4.1 13
Pulse Width Distortion /tPLH - tPHL/ PWD 0.2 4.5 ns VDD 5 V ±10%: See Figure 4.1 13
Propagation Delay Skew tPSK(P-P) 2 4.5 ns VDD 5 V ±10%: note 2, between units at same supply, load, TA 13
Channel-Channel Skew tPSK 0.4 2.5 ns VDD 5 V ±10% 13
Output Rise Time tr 2.5 4 ns VDD 5 V ±10%: CL = 15 pF 13
Output Fall Time tf 2.5 4 ns VDD 5 V ±10%: CL = 15 pF 13
Common Mode Transient Immunity CMTI 35 50 kV/µs VI = VDD or 0 V; VCM = 1500 V 14
Startup Time tSU 15 40 µs Note 3: from power applied to valid data at output 14
10 Mbps Supply Current VDD2 (3.3 V table) 5 7 mA VDD 3.3 V ±10%: All inputs 5 MHz square wave, CI = 15 pF 17
100 Mbps Supply Current VDD2 (3.3 V table) 18.3 23.8 mA VDD 3.3 V ±10%: All inputs 50 MHz square wave, CI = 15 pF 17
10 Mbps Supply Current VDD2 (2.5 V table) 4.6 6.4 mA VDD 2.5 V ±5%: All inputs 5 MHz square wave, CI = 15 pF 20
100 Mbps Supply Current VDD2 (2.5 V table) 14.7 19.1 mA VDD 2.5 V ±5%: All inputs 50 MHz square wave, CI = 15 pF 20
Propagation Delay (2.5 V table) tPHL, tPLH 5 8 14 ns VDD 2.5 V ±5%: See Figure 4.1 21
Pulse Width Distortion (2.5 V table) PWD 0.2 5 ns VDD 2.5 V ±5%: See Figure 4.1 21
Propagation Delay Skew (2.5 V table) tPSK(P-P) 2 5 ns VDD 2.5 V ±5%: note 2, between units 21
IC Junction-to-Air Thermal Resistance θJA 100 °C/W WB SOIC-16 package 24

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32

CAD (KiCad official)

  • Symbol: SI8660BD-B-ISR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: si8660bd-b-isr-etched.step / si8660bd-b-isr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8660bd-b-isr.step / si8660bd-b-isr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (42 pp, sha256 aea8c0805c804419, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF