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SI8652ED-B-ISR

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Skyworks Solutions Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI8652ED-B-ISR

Skyworks Solutions · Digital Isolators · SOIC-16-300mil

SI8652ED-B-ISR from Skyworks Solutions, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply; the device is powered for 2.5 V < VDD < 5.5 V and requires a 0.1 μF bypass capacitor between VDD1 and GND1 placed as close as possible to the package.
2 A1 input Side 1 digital input with Schmitt trigger input for high noise immunity.
3 A2 input Side 1 digital input with Schmitt trigger input for high noise immunity.
4 A3 input Side 1 digital input with Schmitt trigger input for high noise immunity.
5 A4 bidirectional Side 1 digital input or output.
6 A5 bidirectional Side 1 digital input or output.
7 EN1 input Side 1 active high enable; when EN1 is low (EN = 0) the output pin is driven into a high-impedance state.
8 GND1 power_in Side 1 ground; the VDD1 bypass capacitor is connected between VDD1 and this pin.
9 GND2 power_in Side 2 ground.
10 EN2 input Side 2 active high enable; when EN2 is low (EN = 0) the output pin is driven into a high-impedance state.
11 B5 bidirectional Side 2 digital input or output.
12 B4 bidirectional Side 2 digital input or output.
13 B3 output Side 2 digital output.
14 B2 output Side 2 digital output.
15 B1 output Side 2 digital output.
16 VDD2 power_in Side 2 power supply; the device is powered for 2.5 V < VDD < 5.5 V and requires a 0.1 μF bypass capacitor between VDD2 and GND2.

Key specifications

Parameter Value
Manufacturer Skyworks Solutions
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Junction Operating Temperature TJ 150 °C 12
Ambient Operating Temperature TA -40 25 125 °C 12
Supply Voltage VDD1 VDD1 2.375 5.5 V 12
Supply Voltage VDD2 VDD2 2.375 5.5 V 12
Storage Temperature TSTG -65 150 °C 25
Ambient Temperature Under Bias TA -40 125 °C 25
Junction Temperature TJ 150 °C 25
Supply Voltage VDD1, VDD2 -0.5 7 V 25
Input Voltage VI -0.5 V 25
Output Voltage VO -0.5 V 25
Output Current Drive Channel IO 10 mA All devices unless otherwise stated 25
Latchup Immunity 100 V/ns Slew rate across GND1 and GND2 25
Lead Solder Temperature 260 °C 10 s 25
Maximum Isolation (Input to Output) 6500 VRMS 1 sec, WB SOIC-16 25
Case Temperature (safety limiting) TS 150 °C VDE 0884-10 safety limiting value 23
Safety Input, Output, or Supply Current (WB SOIC-16) IS 220 mA θJA = 100 °C/W (WB SOIC-16); VI = 5.5 V, TJ = 150 °C, TA = 25 °C 23
Device Power Dissipation (safety limiting) PD 415 mW 23
IC Junction-to-Air Thermal Resistance (WB SOIC-16) θJA 100 °C/W 24
VDD Undervoltage Threshold (rising) VDDUV+ 1.95 2.24 2.375 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; VDD1, VDD2 rising 12
VDD Undervoltage Threshold (falling) VDDUV- 1.88 2.16 2.325 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; VDD1, VDD2 falling 12
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 12
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; All inputs rising 12
Negative-Going Input Threshold VT- 1 1.23 1.4 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; All inputs falling 12
Input Hysteresis VHYS 0.38 0.44 0.5 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 12
High Level Input Voltage VIH 2 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 12
Low Level Input Voltage VIL 0.8 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 12
High Level Output Voltage VOH 4.8 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; loh = -4 mA 12
Low Level Output Voltage VOL 0.2 0.4 V VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; lol = 4 mA 12
Input Leakage Current IL -10 10 μA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 12
DC Supply Current VDD1 (Si8652Ex) 2 3 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs 0 V or at supply; VI = 0(Bx), 1(Ex) 13
DC Supply Current VDD2 (Si8652Ex) 2.4 3.6 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs 0 V or at supply; VI = 0(Bx), 1(Ex) 13
DC Supply Current VDD1 (Si8652Ex) 5.6 7.8 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs 0 V or at supply; VI = 1(Bx), 0(Ex) 13
DC Supply Current VDD2 (Si8652Ex) 5 7.5 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs 0 V or at supply; VI = 1(Bx), 0(Ex) 13
1 Mbps Supply Current VDD1 (Si8652Bx, Ex) 4 5.6 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs = 500 kHz square wave, CI = 15 pF on all outputs 13
1 Mbps Supply Current VDD2 (Si8652Bx, Ex) 4 5.6 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs = 500 kHz square wave, CI = 15 pF on all outputs 13
10 Mbps Supply Current VDD1 (Si8652Bx, Ex) 4.6 6.4 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs = 5 MHz square wave, CI = 15 pF on all outputs 13
10 Mbps Supply Current VDD2 (Si8652Bx, Ex) 4.9 6.8 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs = 5 MHz square wave, CI = 15 pF on all outputs 13
100 Mbps Supply Current VDD1 (Si8652Bx, Ex) 11.7 15.2 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs = 50 MHz square wave, CI = 15 pF on all outputs 14
100 Mbps Supply Current VDD2 (Si8652Bx, Ex) 15 19.5 mA VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; all inputs = 50 MHz square wave, CI = 15 pF on all outputs 14
Maximum Data Rate 0 150 Mbps VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 14
Minimum Pulse Width 5 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 14
Propagation Delay tPHL, tPLH 5 8 13 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; See Figure 4.2 14
Pulse Width Distortion PWD 0.2 4.5 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; /tPLH, tPHL/, See Figure 4.2 14
Propagation Delay Skew tPSK(P-P) 2 4.5 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 14
Channel-Channel Skew tPSK 0.4 2.5 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 14
Output Rise Time tr 2.5 4 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; CL = 15 pF 14
Output Fall Time tf 2.5 4 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; CL = 15 pF 14
Common Mode Transient Immunity CMTI 35 50 kV/μs VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; VI = VDD or 0 V, VCM = 1500 V 14
Enable to Data Valid ten1 6 11 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; See Figure 4.1 14
Enable to Data Tri-State ten2 8 12 ns VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C; See Figure 4.1 14
Start-up Time tSU 15 40 μs VDD1=VDD2=5 V ±10%, TA=-40 to 125 °C 14

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32

CAD (KiCad official)

  • Symbol: SI8652ED-B-ISR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: si8652ed-b-isr-etched.step / si8652ed-b-isr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8652ed-b-isr.step / si8652ed-b-isr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Skyworks Solutions datasheet (43 pp, sha256 09d461e7e459e538, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF