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SI8642BB-B-IS1

Public Made by Adom

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SILICON LABS Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI8642BB-B-IS1

SILICON LABS · Digital Isolators · SOIC-16

SI8642BB-B-IS1 from SILICON LABS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, which needs a 0.1 µF bypass capacitor to GND1 placed as close as possible to the package.
2 GND1 power_in Side 1 ground; for narrow-body devices this pin must be externally connected to ground.
3 A1 input Side 1 digital input.
4 A2 input Side 1 digital input.
5 A3 bidirectional Side 1 digital input or output.
6 A4 bidirectional Side 1 digital input or output.
7 EN1 input Side 1 active high enable (EN1 on Si8642; NC only on Si8640/45).
8 GND1 power_in Side 1 ground; for narrow-body devices this pin must be externally connected to ground.
9 GND2 power_in Side 2 ground; for narrow-body devices this pin must be connected to external ground.
10 EN2/NC input Side 2 active high enable (EN2 on Si8642; NC only on Si8645).
11 B4 bidirectional Side 2 digital input or output.
12 B3 bidirectional Side 2 digital input or output.
13 B2 output Side 2 digital output.
14 B1 output Side 2 digital output.
15 GND2 power_in Side 2 ground; for narrow-body devices this pin must be connected to external ground.
16 VDD2 power_in Side 2 power supply, which needs a 0.1 µF bypass capacitor to GND2 placed as close as possible to the package.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Operating Temperature TA -40 25 125 °C Note 1: maximum ambient depends on data frequency, output loading, channel count and supply voltage 12
Supply Voltage VDD1 VDD1 2.375 5.5 V 12
Supply Voltage VDD2 VDD2 2.375 5.5 V 12
Junction Operating Temperature TJ 150 °C 12
Storage Temperature TSTG -65 150 °C VDE certifies storage temperature from -40 to 150 °C 27
Operating Temperature TA -40 125 °C 27
Junction Temperature TJ 150 °C 27
Supply Voltage VDD1, VDD2 -0.5 7 V 27
Input Voltage VI -0.5 V Max printed as VDD + 0.5 V 27
Output Voltage VO -0.5 V Max printed as VDD + 0.5 V 27
Output Current Drive Channel IO 10 mA 27
Lead Solder Temperature 260 °C 10 s 27
Output Impedance Tolerance ZO -40 40 % Nominal output impedance of isolator driver channel approximately 50 Ω, ±40% 25
VDD Undervoltage Threshold rising VDDUV+ 1.95 2.24 2.375 V VDD1, VDD2 rising; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
VDD Undervoltage Threshold falling VDDUV- 1.88 2.16 2.325 V VDD1, VDD2 falling; VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = -40 to 125 °C 12
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V All inputs rising; VDD1 = 5 V ±10%, VDD2 = 5 V ±10% 12
Negative-Going Input Threshold VT- 1 1.23 1.4 V All inputs falling; VDD1 = 5 V ±10%, VDD2 = 5 V ±10% 12
Input Hysteresis VHYS 0.38 0.44 0.5 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10% 12
High Level Input Voltage VIH 2 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10% 12
Low Level Input Voltage VIL 0.8 V VDD1 = 5 V ±10%, VDD2 = 5 V ±10% 12
High Level Output Voltage VOH 4.8 V IOH = -4 mA; min printed as VDD1, VDD2, 0.4 12
Low Level Output Voltage VOL 0.2 0.4 V IOL = 4 mA; VDD1 = 5 V ±10%, VDD2 = 5 V ±10% 12
Input Leakage Current IL -10 10 µA Si864xxA/B/C/D 12
Enable Input Current IENH, IENL 2 µA VENx = VIH or VIL; Si864xxA/B/C/D 12
DC Supply Current VDD1 at VI=0(Bx) 1.8 2.9 mA Si8642Bx; all inputs 0 V or at supply; VDD1 = 5 V ±10% 13
DC Supply Current VDD2 at VI=0(Bx) 1.8 2.9 mA Si8642Bx; all inputs 0 V or at supply; VDD2 = 5 V ±10% 13
DC Supply Current VDD1 at VI=1(Bx) 4.4 6.6 mA Si8642Bx; all inputs 0 V or at supply; VDD1 = 5 V ±10% 13
DC Supply Current VDD2 at VI=1(Bx) 4.4 6.6 mA Si8642Bx; all inputs 0 V or at supply; VDD2 = 5 V ±10% 13
1 Mbps Supply Current VDD1 3.3 4.6 mA Si8642Bx; all inputs 500 kHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10% 13
1 Mbps Supply Current VDD2 3.3 4.6 mA Si8642Bx; all inputs 500 kHz square wave, CI = 15 pF on all outputs; VDD2 = 5 V ±10% 13
10 Mbps Supply Current VDD1 3.9 5.4 mA Si8642Bx; all inputs 5 MHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10% 13
10 Mbps Supply Current VDD2 3.9 5.4 mA Si8642Bx; all inputs 5 MHz square wave, CI = 15 pF on all outputs; VDD2 = 5 V ±10% 13
100 Mbps Supply Current VDD1 11 14.3 mA Si8642Bx; all inputs 50 MHz square wave, CI = 15 pF on all outputs; VDD1 = 5 V ±10% 14
100 Mbps Supply Current VDD2 11 14.3 mA Si8642Bx; all inputs 50 MHz square wave, CI = 15 pF on all outputs; VDD2 = 5 V ±10% 14
Maximum Data Rate 0 150 Mbps Si864xBx, Ex 14
Minimum Pulse Width 5 ns Si864xBx, Ex 14
Propagation Delay tPHL, tPLH 5 8 13 ns See Figure 4.2 Propagation Delay Timing; VDD = 5 V ±10% 14
Pulse Width Distortion PWD 0.2 4.5 ns /tPLH, tPHL/; VDD = 5 V ±10% 14
Propagation Delay Skew tPSK(P-P) 2 4.5 ns VDD = 5 V ±10% 14
Channel-Channel Skew tPSK 0.4 2.5 ns VDD = 5 V ±10% 14
Output Rise Time tr 2.5 4 ns CL = 15 pF 14
Output Fall Time tf 2.5 4 ns CL = 15 pF 14
Common Mode Transient Immunity CMTI 35 50 kV/µs Si86xxxA/B/C/D; VI = VDD or 0 V, VCM = 1500 V 14
Enable to Data Valid ten1 6 11 ns See Figure 4.1 ENABLE Timing Diagram 14
Enable to Data Tri-State ten2 8 12 ns See Figure 4.1 ENABLE Timing Diagram 14
Input power loss to valid default output tSD 8 12 ns See Figure 3.1 Device Behavior during Normal Operation 15
Start-up Time tSU 15 40 µs Time from application of power to valid data at output 15
Input Bypass Capacitor 0.1 µF Between VDD1 and GND1 and between VDD2 and GND2; placed as close as possible to package 10
Optional Series Termination Resistor 50 300 Ω Optional, in series with inputs and outputs if system is excessively noisy 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Package Outline (16-Pin Wide Body SOIC) silabs.com / Building a more connected world. Rev. 2.15 / 29 29

CAD (KiCad official)

  • Symbol: SI8642BB-B-IS1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: si8642bb-b-is1-etched.step / si8642bb-b-is1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8642bb-b-is1.step / si8642bb-b-is1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (44 pp, sha256 2425141c8d33cf85, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF