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SI8641BD-B-ISR

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SKYWORKS SILICON LABS Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI8641BD-B-ISR

SKYWORKS SILICON LABS · Digital Isolators · SOIC-16-300mil

SI8641BD-B-ISR from SKYWORKS SILICON LABS, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, operating from 2.5 V to 5.5 V and requiring a 0.1 µF bypass capacitor to GND1.
2 GND1 power_in Side 1 ground.
3 A1 input Side 1 digital input with Schmitt trigger input for high noise immunity.
4 A2 input Side 1 digital input with Schmitt trigger input for high noise immunity.
5 A3 bidirectional Side 1 digital input or output.
6 A4 bidirectional Side 1 digital input or output.
7 EN1 input Side 1 active high enable; when EN is low the output is driven to high impedance (Hi-Z).
8 GND1 power_in Side 1 ground.
9 GND2 power_in Side 2 ground.
10 EN2 input Side 2 active high enable; when EN is low the output is driven to high impedance (Hi-Z).
11 B4 bidirectional Side 2 digital input or output.
12 B3 bidirectional Side 2 digital input or output.
13 B2 output Side 2 digital output.
14 B1 output Side 2 digital output.
15 GND2 power_in Side 2 ground.
16 VDD2 power_in Side 2 power supply, operating from 2.5 V to 5.5 V and requiring a 0.1 µF bypass capacitor to GND2.

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Operating Temperature (recommended) TA -40 25 125 °C Max depends on data frequency, output loading, channel count and supply voltage 12
Junction Operating Temperature TJ 150 °C 12
Supply Voltage VDD1 VDD1 2.375 5.5 V 12
Supply Voltage VDD2 VDD2 2.375 5.5 V 12
VDD Undervoltage Threshold (rising) VDDUV+ 1.95 2.24 2.375 V VDD1, VDD2 rising; 5 V ±10% 12
VDD Undervoltage Threshold (falling) VDDUV- 1.88 2.16 2.325 V VDD1, VDD2 falling; 5 V ±10% 12
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 5 V ±10% 12
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V All inputs rising; 5 V ±10% 12
Negative-Going Input Threshold VT- 1 1.23 1.4 V All inputs falling; 5 V ±10% 12
Input Hysteresis VHYS 0.38 0.44 0.5 V 5 V ±10% 12
High Level Input Voltage VIH 2 V 5 V ±10% 12
Low Level Input Voltage VIL 0.8 V 5 V ±10% 12
High Level Output Voltage VOH 4.8 V IOH = -4 mA; VDD1, VDD2, 0.4 minimum as printed; 5 V ±10% 12
Low Level Output Voltage VOL 0.2 0.4 V IOL = 4 mA; 5 V ±10% 12
Input Leakage Current (Si864xxA/B/C/D) IL -10 10 µA Si864xxA/B/C/D (±10 µA); Si864xxT is ±15 µA 12
Enable Input Current (Si864xxA/B/C/D) IENH, IENL 2 µA VENx = VIH or VIL; Si864xxT max is 10.0 µA 12
DC Supply Current VDD1 (Si8641Bx) 1.4 2.2 mA All inputs 0 V or at supply; VI = 0 (Bx) 13
DC Supply Current VDD2 (Si8641Bx) 2.3 3.7 mA All inputs 0 V or at supply; VI = 0 (Bx) 13
DC Supply Current VDD1 (Si8641Bx) 5.2 7.8 mA All inputs 0 V or at supply; VI = 1 (Bx) 13
DC Supply Current VDD2 (Si8641Bx) 3.6 5.4 mA All inputs 0 V or at supply; VI = 1 (Bx) 13
1 Mbps Supply Current VDD1 (Si8641Bx) 3.4 4.8 mA All inputs = 500 kHz square wave, CI = 15 pF on all outputs 13
1 Mbps Supply Current VDD2 (Si8641Bx) 3.3 4.6 mA All inputs = 500 kHz square wave, CI = 15 pF on all outputs 13
10 Mbps Supply Current VDD1 (Si8641Bx) 3.7 5.2 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs 13
10 Mbps Supply Current VDD2 (Si8641Bx) 4.1 5.8 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs 13
100 Mbps Supply Current VDD1 (Si8641Bx) 7.3 9.8 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs 14
100 Mbps Supply Current VDD2 (Si8641Bx) 14.3 18.5 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs 14
Maximum Data Rate 0 150 Mbps Si864xBx, Ex; 5 V ±10% 14
Minimum Pulse Width 5 ns 5 V ±10% 14
Propagation Delay tPHL, tPLH 5 8 13 ns See Figure 4.2; 5 V ±10% 14
Pulse Width Distortion /tPLH, tPHL/ PWD 0.2 4.5 ns See Figure 4.2; 5 V ±10% 14
Propagation Delay Skew tPSK(P-P) 2 4.5 ns 5 V ±10% 14
Channel-Channel Skew tPSK 0.4 2.5 ns 5 V ±10% 14
Output Rise Time tr 2.5 4 ns CL = 15 pF 14
Output Fall Time tf 2.5 4 ns CL = 15 pF 14
Common Mode Transient Immunity (Si86xxxA/B/C/D) CMTI 35 50 kV/µs VI = VDD or 0 V; VCM = 1500 V 14
Enable to Data Valid ten 6 11 ns See Figure 4.1 14
Enable to Data Tri-State ten 8 12 ns See Figure 4.1 14
Input Power Loss to Valid Default Output tSD 8 12 ns See Figure 3.1; 5 V ±10% 15
Start-up Time tSU 15 40 µs Time from VDD application to valid output data 15
Storage Temperature TSTG -65 150 °C 27
Operating Temperature TA -40 125 °C 27
Junction Temperature TJ 150 °C 27
Supply Voltage VDD1, VDD2 VDD1, VDD2 -0.5 7 V 27
Input Voltage VI (max VDD + 0.5 V) VI -0.5 V Maximum printed as VDD + 0.5 V 27
Output Voltage VO (max VDD + 0.5 V) VO -0.5 V Maximum printed as VDD + 0.5 V 27
Output Current Drive Channel IO 10 mA 27
Lead Solder Temperature 260 °C 10 s 27
Maximum Isolation (Input to Output) 6500 VRMS 1 s; WB SOIC-16 package 27
IC Junction-to-Air Thermal Resistance θJA 100 °C/W WB SOIC-16 package 26
Case Temperature (VDE safety limit) TS 150 °C WB SOIC-16 package 25
Safety Input, Output, or Supply Current IS 220 mA θJA = 100 °C/W (WB SOIC-16); VI = 5.5 V, TJ = 150 °C, TA = 25 °C 25
Device Power Dissipation (VDE safety limit) PD 275 mW VDD1 = VDD2 = 5.5 V; TJ = 150 °C; CL = 15 pF; 150 Mbps 25

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Package Outline (16-Pin Wide Body SOIC) silabs.com / Building a more connected world. Rev. 2.15 / 29 29

CAD (KiCad official)

  • Symbol: SI8641BD-B-ISR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: si8641bd-b-isr-etched.step / si8641bd-b-isr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8641bd-b-isr.step / si8641bd-b-isr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (44 pp, sha256 2425141c8d33cf85, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF