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SI8621AB-B-IS

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SILICON LABS Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI8621AB-B-IS

SILICON LABS · Digital Isolators · SOIC-8

SI8621AB-B-IS from SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, operating range 2.5 to 5.5 V (absolute maximum 7.0 V).
2 A1 bidirectional Side 1 digital input or output.
3 A2 bidirectional Side 1 digital input or output.
4 GND1 power_in Side 1 ground.
5 GND2 power_in Side 2 ground.
6 B2 bidirectional Side 2 digital input or output.
7 B1 bidirectional Side 2 digital input or output.
8 VDD2 power_in Side 2 power supply, operating range 2.5 to 5.5 V (absolute maximum 7.0 V).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Operating Temperature TA -40 25 125 ºC 9
Supply Voltage VDD1 VDD1 2.5 5.5 V 9
Supply Voltage VDD2 VDD2 2.5 5.5 V 9
Storage Temperature TSTG -65 150 ºC 29
Ambient Temperature Under Bias TA -40 125 ºC 29
Junction Temperature TJ 150 °C 29
Supply Voltage VDD1, VDD2 -0.5 7 V 29
Input Voltage VI -0.5 V max printed as VDD + 0.5 V 29
Output Voltage VO -0.5 V max printed as VDD + 0.5 V 29
Output Current Drive Channel (all devices unless otherwise stated) IO 10 mA All devices unless otherwise stated 29
Output Current Drive Channel (Si86xxxA-x-xx devices) IO 22 mA All Si86xxxA-x-xx devices 29
Maximum Isolation (Input to Output) 4500 VRMS 1 sec, NB SOIC-8 29
Lead Solder Temperature 260 ºC 10 s 29
Junction-to-Air Thermal Resistance θJA 140 ºC/W NB SOIC-8 27
VDD Undervoltage Threshold (rising) VDDUV+ 1.95 2.24 2.375 V VDD1, VDD2 rising 9
VDD Undervoltage Threshold (falling) VDDUV- 1.88 2.16 2.325 V VDD1, VDD2 falling 9
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 9
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V All inputs rising 9
Negative-Going Input Threshold VT- 1 1.23 1.4 V All inputs falling 9
Input Hysteresis VHYS 0.38 0.44 0.5 V 9
High Level Input Voltage VIH 2 V 9
Low Level Input Voltage VIL 0.8 V 9
High Level Output Voltage (5 V) VOH 4.8 V Ioh = -4 mA; min printed as VDD1,VDD2, 0.4; VDD = 5 V±10% 9
High Level Output Voltage (3.3 V) VOH 3.1 V Ioh = -4 mA; min printed as VDD1, VDD2, 0.4; VDD = 3.3 V±10% 15
High Level Output Voltage (2.5 V) VOH 2.3 V Ioh = -4 mA; min printed as VDD1,VDD2, 0.4; VDD = 2.5 V±5% 20
Low Level Output Voltage VOL 0.2 0.4 V Iol = 4 mA 9
Input Leakage Current IL -10 10 µA 9
Output Impedance ZO 50 Ω 9
Enable Input High Current IENH 2 µA VENx = VIH 9
Enable Input Low Current IENL 2 µA VENx = VIL 9
DC Supply Current VDD1, input 0 IDD1 1.2 1.9 mA Si8621Ax, VI = 0 10
DC Supply Current VDD2, input 0 IDD2 1.2 1.9 mA Si8621Ax, VI = 0 10
DC Supply Current VDD1, input 1 IDD1 2.4 3.8 mA Si8621Ax, VI = 1 10
DC Supply Current VDD2, input 1 IDD2 2.4 3.8 mA Si8621Ax, VI = 1 10
1 Mbps Supply Current VDD1 IDD1 1.9 2.9 mA Si8621Ax, All inputs = 500 kHz square wave, CI = 15 pF on all outputs 12
1 Mbps Supply Current VDD2 IDD2 1.9 2.9 mA Si8621Ax, All inputs = 500 kHz square wave, CI = 15 pF on all outputs 12
Maximum Data Rate 0 1 Mbps 13
Minimum Pulse Width 250 ns 13
Propagation Delay tPHL, tPLH 35 ns See Figure 4.2 Propagation Delay Timing 13
Pulse Width Distortion /tPLH, tPHL/ PWD 25 ns See Figure 4.2 Propagation Delay Timing 13
Propagation Delay Skew tPSK(P-P) 40 ns 13
Channel-Channel Skew tPSK 35 ns 13
Output Rise Time tr 2.5 4 ns CL = 15 pF, See Figure 4.2 13
Output Fall Time tf 2.5 4 ns CL = 15 pF, See Figure 4.2 13
Common Mode Transient Immunity CMTI 35 50 kV/µs VI = VDD or 0 V, VCM = 1500 V 13
Enable to Data Valid ten1 6 11 ns See Figure 4.1 ENABLE Timing Diagram 13
Enable to Data Tri-State ten2 8 12 ns See Figure 4.1 ENABLE Timing Diagram 13
Start-up Time tSU 15 40 µs 14
Peak eye diagram jitter tJIT(PK) 350 ps See Figure 2.2 Modulation Scheme 13
Capacitance (Input-Output) ΧIO 2 pF f = 1 ΜΗz, NB SOIC-8 26
Input Capacitance CI 4 pF NB SOIC-8, measured from input pin to ground 26

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 38

CAD (KiCad official)

  • Symbol: SI8621AB-B-IS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: si8621ab-b-is-etched.step / si8621ab-b-is-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8621ab-b-is.step / si8621ab-b-is.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (47 pp, sha256 918e2e1a50310d63, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF