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SI8620BB-B-ISR

Public Made by Adom

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SILICON LABS Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SI8620BB-B-ISR

SILICON LABS · Digital Isolators · SOIC-8

SI8620BB-B-ISR from SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, operating range 2.5-5.5 V, with a 0.1 µF bypass capacitor to GND1 placed close to the package.
2 A1 input Side 1 digital input (channel 1 of the Si8620, which has two inputs on the VDD1 side), with a Schmitt trigger input.
3 A2 input Side 1 digital input (channel 2 of the Si8620, which has two inputs on the VDD1 side), with a Schmitt trigger input.
4 GND1 power_in Side 1 ground.
5 GND2 power_in Side 2 ground.
6 B2 output Side 2 digital output for channel 2, with nominal output impedance of about 50 Ω ±40%.
7 B1 output Side 2 digital output for channel 1, with nominal output impedance of about 50 Ω ±40%.
8 VDD2 power_in Side 2 power supply, operating range 2.5-5.5 V, with a 0.1 µF bypass capacitor to GND2 placed close to the package.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD1 VDD1 2.5 5.5 V 11
Supply Voltage VDD2 VDD2 2.5 5.5 V 11
Storage Temperature TSTG -65 150 °C 27
Operating Temperature TA -40 125 °C 27
Junction Temperature TJ 150 °C 27
Supply Voltage VDD1, VDD2 -0.5 7 V 27
Input Voltage VI -0.5 V Max is VDD + 0.5 V 27
Output Voltage VO -0.5 V Max is VDD + 0.5 V 27
Output Current Drive Channel IO 10 mA 27
Lead Solder Temperature 260 °C 10 s 27
Junction-to-Air Thermal Resistance θJA 140 °C/W NB SOIC-8 26
VDD Undervoltage Threshold rising VDDUV+ 1.95 2.24 2.375 V VDD1, VDD2 rising 11
VDD Undervoltage Threshold falling VDDUV- 1.88 2.16 2.325 V VDD1, VDD2 falling 11
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 11
Positive-Going Input Threshold (5 V / 3.3 V tables) VT+ 1.4 1.67 1.9 V All inputs rising 11
Negative-Going Input Threshold (5 V / 3.3 V tables) VT- 1 1.23 1.4 V All inputs falling 11
Input Hysteresis (5 V / 3.3 V tables) VHYS 0.38 0.44 0.5 V 11
High Level Input Voltage VIH 2 V 11
Low Level Input Voltage VIL 0.8 V 11
High Level Output Voltage (5 V table) VOH 4.8 V loh = -4 mA; min is VDD1, VDD2, 0.4 11
Low Level Output Voltage VOL 0.2 0.4 V lol = 4 mA 11
Input Leakage Current IL -10 10 µA Si86xxxB/C/D 11
DC Supply Current Si8620Bx VDD1 (5 V table) IDD1 0.8 1.4 mA VI = 0 (Bx) 12
DC Supply Current Si8620Bx VDD2 (5 V table) IDD2 1.4 2.2 mA VI = 0 (Bx) 12
DC Supply Current Si8620Bx VDD1 (5 V table) IDD1 3.3 5.3 mA VI = 1 (Bx) 12
1 Mbps Supply Current Si8620Bx VDD1 IDD1 2.1 3.1 mA All inputs = 500 kHz square wave, CI = 15 pF on all outputs 12
1 Mbps Supply Current Si8620Bx VDD2 IDD2 1.6 2.4 mA All inputs = 500 kHz square wave, CI = 15 pF on all outputs 12
10 Mbps Supply Current Si8620Bx VDD1 (5 V table) IDD1 2.1 3.1 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs 13
10 Mbps Supply Current Si8620Bx VDD2 (5 V table) IDD2 2.2 3.3 mA All inputs = 5 MHz square wave, CI = 15 pF on all outputs 13
100 Mbps Supply Current Si8620Bx VDD1 IDD1 2.1 3.1 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs 13
100 Mbps Supply Current Si8620Bx VDD2 (5 V table) IDD2 8.9 12.5 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs 13
Maximum Data Rate 0 150 Mbps 13
Minimum Pulse Width 5 ns 13
Propagation Delay (5 V / 3.3 V tables) tPHL, tPLH 5 8 13 ns See Figure 4.1 Propagation Delay Timing 13
Pulse Width Distortion (5 V / 3.3 V tables) PWD 0.2 4.5 ns /tPLH, tPHL/; See Figure 4.1 Propagation Delay Timing 13
Propagation Delay Skew (5 V / 3.3 V tables) tPSK(P-P) 2 4.5 ns 13
Channel-Channel Skew tPSK 0.4 2.5 ns 13
Output Rise Time tr 2.5 4 ns CL = 15 pF; See Figure 4.1 Propagation Delay Timing 14
Output Fall Time tf 2.5 4 ns CL = 15 pF; See Figure 4.1 Propagation Delay Timing 14
Common Mode Transient Immunity CMTI 35 50 kV/µs Si86xxxB/C/D; VI = VDD or 0 V, VCM = 1500 V 14
Start-up Time tSU 15 40 µs 14
High Level Output Voltage (3.3 V table) VOH 3.1 V loh = -4 mA; min is VDD1, VDD2, 0.4 16
High Level Output Voltage (2.5 V table) VOH 2.3 V loh = -4 mA; min is VDD1, VDD2, 0.4 19
100 Mbps Supply Current Si8620Bx VDD2 (3.3 V table) IDD2 6.3 8.8 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs 18
100 Mbps Supply Current Si8620Bx VDD2 (2.5 V table) IDD2 5.1 7.1 mA All inputs = 50 MHz square wave, CI = 15 pF on all outputs 21
Positive-Going Input Threshold (2.5 V table) VT+ 1.6 1.9 V All inputs rising 19
Negative-Going Input Threshold (2.5 V table) VT- 1.1 1.4 V All inputs falling 19
Input Hysteresis (2.5 V table) VHYS 0.4 0.45 0.5 V 19
Propagation Delay (2.5 V table) tPHL, tPLH 5 8 14 ns See Figure 4.1 Propagation Delay Timing 21
Pulse Width Distortion (2.5 V table) PWD 0.2 5 ns /tPLH, tPHL/; See Figure 4.1 Propagation Delay Timing 21
Propagation Delay Skew (2.5 V table) tPSK(P-P) 2 5 ns 21
Output Impedance ZO 50 Ω 11
Peak Eye Diagram Jitter tJIT(PK) 350 ps See Figure 2.3 Eye Diagram 14
Capacitance (Input-Output) CIO 2 pF f = 1 MHz; NB SOIC-8 24
Input Capacitance CI 4 pF Measured from input pin to ground; NB SOIC-8 24

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Pin Descriptions (Wide-Body SOIC) silabs.com / Building a more connected world. Rev. 1.75 / 28 28

CAD (KiCad official)

  • Symbol: SI8620BB-B-ISR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: si8620bb-b-isr-etched.step / si8620bb-b-isr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8620bb-b-isr.step / si8620bb-b-isr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (39 pp, sha256 f3d0f95ee801f87b, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF