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SI8620BB-B-IS

Public Made by Adom

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SILICON LABS Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI8620BB-B-IS

SILICON LABS · Digital Isolators · SOIC-8

SI8620BB-B-IS from SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply; a 0.1 µF bypass capacitor is required between VDD1 and GND1, placed as close as possible to the package.
2 A1 bidirectional Side 1 digital input or output.
3 A2 bidirectional Side 1 digital input or output.
4 GND1 power_in Side 1 ground.
5 GND2 power_in Side 2 ground.
6 B2 bidirectional Side 2 digital input or output.
7 B1 bidirectional Side 2 digital input or output.
8 VDD2 power_in Side 2 power supply; a 0.1 µF bypass capacitor is required between VDD2 and GND2, placed as close as possible to the package.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Leakage Current (Si86xxxB/C/D) IL -10 10 µA Si86xxxB/C/D 11
Low Level Input Voltage VIL 0.8 V 11
High Level Input Voltage VIH 2 V 11
VDD Undervoltage Threshold (rising) VDDUV+ 1.95 2.24 2.375 V VDD1, VDD2 rising 11
VDD Undervoltage Threshold (falling) VDDUV- 1.88 2.16 2.325 V VDD1, VDD2 falling 11
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 11
Positive-Going Input Threshold VT+ 1.4 1.67 1.9 V All inputs rising 11
Negative-Going Input Threshold VT- 1 1.23 1.4 V All inputs falling 11
Input Hysteresis VHYS 0.38 0.44 0.5 V 11
Low Level Output Voltage VOL 0.2 0.4 V lol = 4 mA 11
High Level Output Voltage VOH 4.8 V loh = -4 mA; printed min is VDD1, VDD2, 0.4 11
Output Impedance ZO 50 Ω nominal, ±40% per footnote 11
DC Supply Current VDD1 (VI = 0 Bx) 0.8 1.4 mA VDD1; all inputs 0 V or at supply; VI = 0 (Bx) 11
DC Supply Current VDD2 (VI = 0 Bx) 1.4 2.2 mA VDD2; all inputs 0 V or at supply; VI = 0 (Bx) 11
DC Supply Current VDD1 (VI = 1 Bx) 3.3 5.3 mA VDD1; all inputs 0 V or at supply; VI = 1 (Bx) 11
DC Supply Current VDD2 (VI = 1 Bx) 1.4 2.2 mA VDD2; all inputs 0 V or at supply; VI = 1 (Bx) 11
1 Mbps Supply Current VDD1 2.1 3.1 mA All inputs 500 kHz square wave, CI = 15 pF 12
1 Mbps Supply Current VDD2 1.6 2.4 mA All inputs 500 kHz square wave, CI = 15 pF 12
10 Mbps Supply Current VDD1 2.1 3.1 mA All inputs 5 MHz square wave, CI = 15 pF 13
10 Mbps Supply Current VDD2 2.2 3.3 mA All inputs 5 MHz square wave, CI = 15 pF 13
100 Mbps Supply Current VDD1 2.1 3.1 mA All inputs 50 MHz square wave, CI = 15 pF 13
100 Mbps Supply Current VDD2 8.9 12.5 mA All inputs 50 MHz square wave, CI = 15 pF 13
Maximum Data Rate 0 150 Mbps 13
Minimum Pulse Width 5 ns 13
Propagation Delay tPHL, tPLH 5 8 13 ns See Figure 4.1 13
Pulse Width Distortion PWD 0.2 4.5 ns /tPLH, tPHL/; See Figure 4.1 13
Propagation Delay Skew tPSK(P-P) 2 4.5 ns 13
Channel-Channel Skew tPSK 0.4 2.5 ns 13
Output Rise Time tr 2.5 4 ns CL = 15 pF 14
Output Fall Time tf 2.5 4 ns CL = 15 pF 14
Peak Eye Diagram Jitter tJIT(PK) 350 ps 14
Common Mode Transient Immunity (Si86xxxB/C/D) CMTI 35 50 kV/µs VI = VDD or 0 V, VCM = 1500 V 14
Start-up Time tSU 15 40 µs 14
Supply Voltage VDD1 VDD1 2.5 5.5 V 11
Supply Voltage VDD2 VDD2 2.5 5.5 V 11
Storage Temperature TSTG -65 150 °C 27
Operating Temperature TA -40 125 °C 27
Junction Temperature TJ 150 °C 27
Supply Voltage VDD1, VDD2 -0.5 7 V 27
Input Voltage VI -0.5 V max printed as VDD + 0.5 27
Output Voltage VO -0.5 V max printed as VDD + 0.5 27
Output Current Drive Channel IO 10 mA 27
Lead Solder Temperature 260 °C 10 s 27
IC Junction-to-Air Thermal Resistance θJA 140 °C/W NB SOIC-8 package 26

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Pin Descriptions (Wide-Body SOIC) silabs.com / Building a more connected world. Rev. 1.75 / 28 28

CAD (KiCad official)

  • Symbol: SI8620BB-B-IS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: si8620bb-b-is-etched.step / si8620bb-b-is-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si8620bb-b-is.step / si8620bb-b-is.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (39 pp, sha256 f3d0f95ee801f87b, retrieved 2026-10-29, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF