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SI8421AB-D-ISR
Public Made by Adomby adom
SILICON LABS Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSI8421AB-D-ISR
SILICON LABS · Digital Isolators · SOIC-8
SI8421AB-D-ISR from SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Side 1 power supply, operating range 2.70 V to 5.5 V, with a bypass capacitor of 1 µF or more recommended to GND1. |
| 2 | A1 | bidirectional | Side 1 digital input or output (channel A1). |
| 3 | A2 | bidirectional | Side 1 digital input or output (channel A2). |
| 4 | GND1 | power_in | Side 1 ground. |
| 5 | GND2 | power_in | Side 2 ground. |
| 6 | B2 | bidirectional | Side 2 digital input or output (channel B2). |
| 7 | B1 | bidirectional | Side 2 digital input or output (channel B1). |
| 8 | VDD2 | power_in | Side 2 power supply, operating range 2.70 V to 5.5 V, with a bypass capacitor of 1 µF or more recommended to GND2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | TA | -40 | 25 | 125 | °C | 150 Mbps, 15 pF, 5 V | 4 |
| Supply Voltage VDD1 | VDD1 | 2.7 | 5.5 | V | 4 | ||
| Supply Voltage VDD2 | VDD2 | 2.7 | 5.5 | V | 4 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 4 | ||
| Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage (Revision D) | VDD1, VDD2 | -0.5 | 6 | V | Revision D | 4 | |
| Input Voltage | VI | -0.5 | V | max is VDD + 0.5 V | 4 | ||
| Output Voltage | VO | -0.5 | V | max is VDD + 0.5 V | 4 | ||
| Output Current Drive Channel | IO | 10 | mA | 4 | |||
| Lead Solder Temperature (10 s) | 260 | °C | 10 s | 4 | |||
| Maximum Isolation Voltage (1 s) | 3600 | VRMS | 1 s | 4 | |||
| IC Junction-to-Air Thermal Resistance | θJA | 140 | °C/W | 16 | |||
| High Level Input Voltage | VIH | 2 | V | VDD1 = VDD2 = 5 V ±10%, TA = -40 to 125 ºC | 5 | ||
| Low Level Input Voltage | VIL | 0.8 | V | VDD1 = VDD2 = 5 V ±10%, TA = -40 to 125 ºC | 5 | ||
| High Level Output Voltage | VOH | 4.8 | V | Ioh = -4 mA; min is VDD1,VDD2, 0.4; 5 V ±10% | 5 | ||
| Low Level Output Voltage | VOL | 0.2 | 0.4 | V | Iol = 4 mA; 5 V ±10% | 5 | |
| Input Leakage Current | IL | -10 | 10 | µA | 5 V ±10% | 5 | |
| Output Impedance | ZO | 85 | Ω | nominal, ±40% per note 1 | 5 | ||
| DC Supply Current VDD1, inputs 0 | IDD1 | 1.3 | 2 | mA | Si8421Ax; All inputs 0 DC; 5 V | 5 | |
| DC Supply Current VDD2, inputs 0 | IDD2 | 1.3 | 2 | mA | Si8421Ax; All inputs 0 DC; 5 V | 5 | |
| DC Supply Current VDD1, inputs 1 | IDD1 | 2.3 | 3.5 | mA | Si8421Ax; All inputs 1 DC; 5 V | 5 | |
| DC Supply Current VDD2, inputs 1 | IDD2 | 2.3 | 3.5 | mA | Si8421Ax; All inputs 1 DC; 5 V | 5 | |
| 1 Mbps Supply Current VDD1 | IDD1 | 1.9 | 2.9 | mA | Si8421Ax; 500 kHz square wave, CI = 15 pF; 5 V | 5 | |
| 1 Mbps Supply Current VDD2 | IDD2 | 1.9 | 2.9 | mA | Si8421Ax; 500 kHz square wave, CI = 15 pF; 5 V | 5 | |
| Maximum Data Rate | 0 | 1 | Mbps | Si8421Ax | 6 | ||
| Minimum Pulse Width | 250 | ns | Si8421Ax | 6 | |||
| Propagation Delay | tPHL, tPLH | 35 | ns | See Figure 1; Si8421Ax | 6 | ||
| Pulse Width Distortion /tPLH - tPHL/ | PWD | 25 | ns | See Figure 1; Si8421Ax | 6 | ||
| Propagation Delay Skew | tPSK(P-P) | 40 | ns | Si8421Ax | 6 | ||
| Channel-Channel Skew | tPSK | 35 | ns | Si8421Ax | 6 | ||
| Output Rise Time | tr | 3.8 | 5 | ns | CL = 15 pF; 5 V ±10% | 7 | |
| Output Fall Time | tf | 2.8 | 3.7 | ns | CL = 15 pF; 5 V ±10% | 7 | |
| Common Mode Transient Immunity | CMTI | 25 | kV/µs | VI = VDD or 0 V | 7 | ||
| Start-up Time | tSU | 15 | 40 | µs | 7 | ||
| High Level Output Voltage (3.3 V) | VOH | 3.1 | V | Ioh = -4 mA; min is VDD1,VDD2, 0.4; 3.3 V ±10% | 8 | ||
| Output Rise Time (3.3 V) | tr | 4.3 | 6.1 | ns | CL = 15 pF; 3.3 V ±10% | 10 | |
| Output Fall Time (3.3 V) | tf | 3 | 4.3 | ns | CL = 15 pF; 3.3 V ±10% | 10 | |
| High Level Output Voltage (2.70 V) | VOH | 2.3 | V | Ioh = -4 mA; min is VDD1,VDD2, 0.4; VDD = 2.70 V | 11 | ||
| Output Rise Time (2.70 V) | tr | 4.8 | 6.5 | ns | CL = 15 pF; VDD = 2.70 V | 13 | |
| Output Fall Time (2.70 V) | tf | 3.2 | 4.6 | ns | CL = 15 pF; VDD = 2.70 V | 13 | |
| Capacitance (Input-Output) | CIO | 1 | pF | f = 1 MHz | 14 | ||
| Input Capacitance | CI | 4 | pF | Measured from input pin to ground | 14 |
CAD (KiCad official)
- Symbol:
SI8421AB-D-ISR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
si8421ab-d-isr-etched.step/si8421ab-d-isr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si8421ab-d-isr.step/si8421ab-d-isr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (30 pp, sha256
630ea949473edada, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).