# SI7972DP-T1-GE3-VB

**VBsemi Elec** · MOSFETs · DFN5x6-8

SI7972DP-T1-GE3-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET 1 (60 V VDS rated device, 17 A ID at TC = 25 °C). |
| 2 | G1 | input | Gate of N-channel MOSFET 1, with VGS absolute maximum of ±20 V. |
| 3 | S2 | passive | Source of N-channel MOSFET 2 (60 V VDS rated device, 17 A ID at TC = 25 °C). |
| 4 | G2 | input | Gate of N-channel MOSFET 2, with VGS absolute maximum of ±20 V. |
| 5 | D2 | passive | Drain of N-channel MOSFET 2, with VDS of 60 V maximum. |
| 6 | D2 | passive | Drain of N-channel MOSFET 2, with VDS of 60 V maximum. |
| 7 | D1 | passive | Drain of N-channel MOSFET 1, with VDS of 60 V maximum. |
| 8 | D1 | passive | Drain of N-channel MOSFET 1, with VDS of 60 V maximum. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | DFN5x6-8 |
| Category | Transistors/Thyristors |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | 60 | V | TA = 25 °C | 1 |
| Gate-source voltage | VGS | -20 |  | 20 | V | TA = 25 °C | 1 |
| Continuous drain current | ID |  |  | 17 | A | TJ = 150 °C, TC = 25 °C | 1 |
| Pulsed drain current | IDM |  |  | 40 | A |  | 1 |
| Source-drain diode current | IS |  |  | 19 | A | TC = 25 °C | 1 |
| Maximum power dissipation | PD |  |  | 22 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD |  |  | 3.6 | W | TA = 25 °C, b, c | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 |  | 150 | °C |  | 1 |
| Soldering peak temperature |  |  |  | 260 | °C | d, e | 1 |
| Junction-to-ambient thermal resistance | RthJA |  | 26 | 35 | °C/W | t ≤ 10 s, b, f | 1 |
| Junction-to-case (drain) thermal resistance | RthJC |  |  | 45.5 | °C/W | Steady state | 1 |
| Drain-source breakdown voltage | VDS | 60 |  |  | V | VGS = 0 V, ID = 250 μA | 2 |
| Gate threshold voltage | VGS(th) | 1.2 |  | 2.7 | V | VDS = VGS, ID = 250 μA | 2 |
| Gate-body leakage | IGSS |  |  | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | 1 | μA | VDS = 60 V, VGS = 0 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | 10 | μA | VDS = 60 V, VGS = 0 V, TJ = 85 °C | 2 |
| On-state drain current | ID(on) | 60 |  |  | A | VDS ≥ 5 V, VGS = 10 V | 2 |
| Gate resistance | Rg | 0.12 | 0.6 | 1.2 | Ω | f = 1 MHz | 2 |
| Total gate charge | Qg |  | 15.2 | 23 | nC | VDS = 30 V, VGS = 10 V, ID = 11 A | 2 |
| Turn-off delay time | td(off) |  | 15 | 30 | ns | VDD = 30 V, RL = 3.45 Ω, ID ≅ 8.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 |
| Fall time | tf |  | 15 | 30 | ns | VDD = 30 V, RL = 3.45 Ω, ID ≅ 8.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 |
| Rise time | tr |  | 25 | 40 | ns | VDD = 30 V, RL = 3.45 Ω, ID ≅ 8.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Turn-off delay time | td(off) |  | 20 | 30 | ns | VDD = 30 V, RL = 3.45 Ω, ID ≅ 8.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Fall time | tf |  | 10 | 15 | ns | VDD = 30 V, RL = 3.45 Ω, ID ≅ 8.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Continuous source-drain diode current | IS |  |  | 8 | A | TC = 25 °C | 2 |
| Pulse diode forward current | ISM |  |  | 40 | A |  | 2 |
| Body diode voltage | VSD |  | 0.8 | 1.2 | V | IS = 8.7 A | 2 |
| Body diode reverse recovery charge | Qrr |  | 30 | 45 | nC | IF = 8.7 A, di/dt = 100 A/μs, TJ = 25 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.032 |  | Ω | VGS = 10 V, ID = 11 A | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.038 |  | Ω | VGS = 4.5 V, ID = 10 A | 2 |
| Forward transconductance | gfs |  | 38 |  | S | VDS = 30 V, ID = 11 A | 2 |
| Input capacitance | Ciss |  | 1050 |  | pF | VDS = 30 V, VGS = 0 V, f = 1 MHz | 2 |
| Output capacitance | Coss |  | 435 |  | pF | VDS = 30 V, VGS = 0 V, f = 1 MHz | 2 |
| Reverse transfer capacitance | Crss |  | 20 |  | pF | VDS = 30 V, VGS = 0 V, f = 1 MHz | 2 |
| VDS temperature coefficient | ΔVDS/TJ |  | 38 |  | mV/°C | ID = 250 μA | 2 |
| VGS(th) temperature coefficient | ΔVGS(th)/TJ |  | -4.9 |  | mV/°C | ID = 250 μA | 2 |
| Gate-source charge | Qgs |  | 4.4 |  | nC | VDS = 30 V, VGS = 4.5 V, ID = 11 A | 2 |
| Gate-drain charge | Qgd |  | 1.3 |  | nC | VDS = 30 V, VGS = 4.5 V, ID = 11 A | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | d. The DFN 5x6 package is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process | 1 |

## CAD (KiCad official)

- Symbol: `SI7972DP-T1-GE3-VB`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN5x6-8 (KiCad packages3D, STEP)
- 3D model files: `si7972dp-t1-ge3-vb-etched.step` / `si7972dp-t1-ge3-vb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si7972dp-t1-ge3-vb.step` / `si7972dp-t1-ge3-vb.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [VBsemi Elec datasheet](docs/si7972dp-t1-ge3-vb-datasheet.pdf) (7 pp, sha256 `214a77253d9fc90d`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/si7972dp-t1-ge3-vb-datasheet.pdf)