component
SI7149ADP-T1-GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SI7149ADP-T1-GE3
Vishay Intertech · MOSFETs · SO-8
SI7149ADP-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET (30 V, -50 A rated package limit); pins 1-3 are all source. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; pins 1-3 are all source. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; pins 1-3 are all source. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; the datasheet gives VGS(th) of -1.2 V to -2.5 V and VGS absolute maximum of ±25 V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -30 | V | 1 | |||
| Gate-Source Voltage | VGS | -25 | 25 | V | 1 | ||
| Continuous Drain Current (TC = 25 °C) | ID | -50 | A | TJ = 150 °C; TC = 25 °C; note d | 1 | ||
| Continuous Drain Current (TC = 70 °C) | ID | -50 | A | TJ = 150 °C; TC = 70 °C; note d | 1 | ||
| Continuous Drain Current (TA = 25 °C) | ID | -23.1 | A | TA = 25 °C; notes a, b | 1 | ||
| Continuous Drain Current (TA = 70 °C) | ID | -18.4 | A | TA = 70 °C; notes a, b | 1 | ||
| Pulsed Drain Current | IDM | -300 | A | t = 100 µs | 1 | ||
| Continuous Source-Drain Diode Current (TC = 25 °C) | IS | -50 | A | TC = 25 °C; note d | 1 | ||
| Continuous Source-Drain Diode Current (TA = 25 °C) | IS | -4.1 | A | TA = 25 °C; notes a, b | 1 | ||
| Avalanche Current | IAS | -25 | A | L = 0.1 mH | 1 | ||
| Single-Pulse Avalanche Energy | EAS | 31.2 | mJ | 1 | |||
| Maximum Power Dissipation (TC = 25 °C) | PD | 48 | W | TC = 25 °C | 1 | ||
| Maximum Power Dissipation (TC = 70 °C) | PD | 31 | W | TC = 70 °C | 1 | ||
| Maximum Power Dissipation (TA = 25 °C) | PD | 5 | W | TA = 25 °C; notes a, b | 1 | ||
| Maximum Power Dissipation (TA = 70 °C) | PD | 3.2 | W | TA = 70 °C; notes a, b | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Soldering Recommendations (Peak Temperature) | 260 | °C | notes e, f | 1 | |||
| Maximum Junction-to-Ambient | RthJA | 21 | 25 | °C/W | t 10 s; notes a, b | 1 | |
| Maximum Junction-to-Ambient (steady state) | RthJA | 70 | °C/W | steady state; note c | 1 | ||
| Maximum Junction-to-Case (steady state) | RthJC | 2.1 | 2.6 | °C/W | steady state | 1 | |
| Drain-Source Breakdown Voltage | VDS | -30 | V | VGS = 0, ID = -250 µA | 2 | ||
| Gate-Source Threshold Voltage | VGS(th) | -1.2 | -2.5 | V | VDS = VGS, ID = -250 µA | 2 | |
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 25 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = -30 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current (TJ = 55 °C) | IDSS | -5 | µA | VDS = -30 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current | ID(on) | -30 | A | VDS -10 V, VGS = -10 V | 2 | ||
| Drain-Source On-State Resistance (VGS = -10 V) | RDS(on) | 0.0042 | 0.0052 | Ω | VGS = -10 V, ID = -15 A | 2 | |
| Drain-Source On-State Resistance (VGS = -4.5 V) | RDS(on) | 0.0076 | 0.0095 | Ω | VGS = -4.5 V, ID = -10 A | 2 | |
| Total Gate Charge (VGS = -10 V) | Qg | 90 | 135 | nC | VDS = -15 V, VGS = -10 V, ID = -10 A | 2 | |
| Total Gate Charge (VGS = -4.5 V) | Qg | 43.1 | 65 | nC | VDS = -15 V, VGS = -4.5 V, ID = -10 A | 2 | |
| Gate Resistance | Rg | 0.5 | 2.4 | 4.8 | Ω | f = 1 MHz | 2 |
| Turn-On Delay Time (VGEN = -10 V) | td(on) | 15 | 30 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 | |
| Rise Time (VGEN = -10 V) | tr | 12 | 24 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 | |
| Turn-Off Delay Time (VGEN = -10 V) | td(off) | 58 | 110 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 | |
| Fall Time (VGEN = -10 V) | tf | 12 | 24 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 | |
| Turn-On Delay Time (VGEN = -4.5 V) | td(on) | 60 | 120 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 | |
| Rise Time (VGEN = -4.5 V) | tr | 60 | 120 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 | |
| Turn-Off Delay Time (VGEN = -4.5 V) | td(off) | 52 | 100 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 | |
| Fall Time (VGEN = -4.5 V) | tf | 26 | 52 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 | |
| Body Diode Voltage | VSD | -0.74 | -1.2 | V | IS = -3 A, VGS = 0 | 2 | |
| Body Diode Reverse Recovery Time | trr | 23 | 46 | ns | IF = -10 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 | |
| Body Diode Reverse Recovery Charge | Qrr | 12 | 24 | nC | IF = -10 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pc | running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board, | 10 | |
| contacts | copper | e. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper | 1 |
CAD (KiCad official)
- Symbol:
SI7149ADP-T1-GE3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
si7149adp-t1-ge3-etched.step/si7149adp-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si7149adp-t1-ge3.step/si7149adp-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (13 pp, sha256
48955304ccdd0d2a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SI7149ADP-T1-GE3
**Vishay Intertech** · MOSFETs · SO-8
SI7149ADP-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET (30 V, -50 A rated package limit); pins 1-3 are all source. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; pins 1-3 are all source. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; pins 1-3 are all source. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; the datasheet gives VGS(th) of -1.2 V to -2.5 V and VGS absolute maximum of ±25 V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; pins 5-8 are all drain and connect to the extended drain pad of the package. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -30 | | | V | | 1 |
| Gate-Source Voltage | VGS | -25 | | 25 | V | | 1 |
| Continuous Drain Current (TC = 25 °C) | ID | -50 | | | A | TJ = 150 °C; TC = 25 °C; note d | 1 |
| Continuous Drain Current (TC = 70 °C) | ID | -50 | | | A | TJ = 150 °C; TC = 70 °C; note d | 1 |
| Continuous Drain Current (TA = 25 °C) | ID | -23.1 | | | A | TA = 25 °C; notes a, b | 1 |
| Continuous Drain Current (TA = 70 °C) | ID | -18.4 | | | A | TA = 70 °C; notes a, b | 1 |
| Pulsed Drain Current | IDM | -300 | | | A | t = 100 µs | 1 |
| Continuous Source-Drain Diode Current (TC = 25 °C) | IS | -50 | | | A | TC = 25 °C; note d | 1 |
| Continuous Source-Drain Diode Current (TA = 25 °C) | IS | -4.1 | | | A | TA = 25 °C; notes a, b | 1 |
| Avalanche Current | IAS | -25 | | | A | L = 0.1 mH | 1 |
| Single-Pulse Avalanche Energy | EAS | | | 31.2 | mJ | | 1 |
| Maximum Power Dissipation (TC = 25 °C) | PD | | | 48 | W | TC = 25 °C | 1 |
| Maximum Power Dissipation (TC = 70 °C) | PD | | | 31 | W | TC = 70 °C | 1 |
| Maximum Power Dissipation (TA = 25 °C) | PD | | | 5 | W | TA = 25 °C; notes a, b | 1 |
| Maximum Power Dissipation (TA = 70 °C) | PD | | | 3.2 | W | TA = 70 °C; notes a, b | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Soldering Recommendations (Peak Temperature) | | | | 260 | °C | notes e, f | 1 |
| Maximum Junction-to-Ambient | RthJA | | 21 | 25 | °C/W | t 10 s; notes a, b | 1 |
| Maximum Junction-to-Ambient (steady state) | RthJA | | | 70 | °C/W | steady state; note c | 1 |
| Maximum Junction-to-Case (steady state) | RthJC | | 2.1 | 2.6 | °C/W | steady state | 1 |
| Drain-Source Breakdown Voltage | VDS | -30 | | | V | VGS = 0, ID = -250 µA | 2 |
| Gate-Source Threshold Voltage | VGS(th) | -1.2 | | -2.5 | V | VDS = VGS, ID = -250 µA | 2 |
| Gate-Source Leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 25 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | µA | VDS = -30 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current (TJ = 55 °C) | IDSS | | | -5 | µA | VDS = -30 V, VGS = 0 V, TJ = 55 °C | 2 |
| On-State Drain Current | ID(on) | -30 | | | A | VDS -10 V, VGS = -10 V | 2 |
| Drain-Source On-State Resistance (VGS = -10 V) | RDS(on) | | 0.0042 | 0.0052 | Ω | VGS = -10 V, ID = -15 A | 2 |
| Drain-Source On-State Resistance (VGS = -4.5 V) | RDS(on) | | 0.0076 | 0.0095 | Ω | VGS = -4.5 V, ID = -10 A | 2 |
| Total Gate Charge (VGS = -10 V) | Qg | | 90 | 135 | nC | VDS = -15 V, VGS = -10 V, ID = -10 A | 2 |
| Total Gate Charge (VGS = -4.5 V) | Qg | | 43.1 | 65 | nC | VDS = -15 V, VGS = -4.5 V, ID = -10 A | 2 |
| Gate Resistance | Rg | 0.5 | 2.4 | 4.8 | Ω | f = 1 MHz | 2 |
| Turn-On Delay Time (VGEN = -10 V) | td(on) | | 15 | 30 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 |
| Rise Time (VGEN = -10 V) | tr | | 12 | 24 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 |
| Turn-Off Delay Time (VGEN = -10 V) | td(off) | | 58 | 110 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 |
| Fall Time (VGEN = -10 V) | tf | | 12 | 24 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -10 V, Rg = 1 | 2 |
| Turn-On Delay Time (VGEN = -4.5 V) | td(on) | | 60 | 120 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 |
| Rise Time (VGEN = -4.5 V) | tr | | 60 | 120 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 |
| Turn-Off Delay Time (VGEN = -4.5 V) | td(off) | | 52 | 100 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 |
| Fall Time (VGEN = -4.5 V) | tf | | 26 | 52 | ns | VDD = -15 V, RL = 1.5, ID = -10 A, VGEN = -4.5 V, Rg = 1 | 2 |
| Body Diode Voltage | VSD | | -0.74 | -1.2 | V | IS = -3 A, VGS = 0 | 2 |
| Body Diode Reverse Recovery Time | trr | | 23 | 46 | ns | IF = -10 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 |
| Body Diode Reverse Recovery Charge | Qrr | | 12 | 24 | nC | IF = -10 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pc | | running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board, | 10 |
| contacts | copper | | e. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper | 1 |
## CAD (KiCad official)
- Symbol: `SI7149ADP-T1-GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `si7149adp-t1-ge3-etched.step` / `si7149adp-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si7149adp-t1-ge3.step` / `si7149adp-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918699122708480) (13 pp, sha256 `48955304ccdd0d2a`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/si7149adp-t1-ge3-datasheet.pdf)