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SI6562CDQ-T1-GE3

Public Made by Adom

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Vishay Intertech MOSFETs, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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SI6562CDQ-T1-GE3

Vishay Intertech · MOSFETs · TSSOP-8

SI6562CDQ-T1-GE3 from Vishay Intertech, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 passive Drain of the N-channel MOSFET (20 V VDS, 6.7 A continuous at TC = 25 °C).
2 S1 passive Source of the N-channel MOSFET, tied internally with pin 3.
3 S1 passive Source of the N-channel MOSFET, tied internally with pin 2.
4 G1 input Gate of the N-channel MOSFET (VGS rated ±12 V, threshold 0.6 to 1.5 V).
5 G2 input Gate of the P-channel MOSFET (VGS rated ±12 V, threshold -0.6 to -1.5 V).
6 S2 passive Source of the P-channel MOSFET, tied internally with pin 7.
7 S2 passive Source of the P-channel MOSFET, tied internally with pin 6.
8 D2 passive Drain of the P-channel MOSFET (-20 V VDS, -6.1 A continuous at TC = 25 °C).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package TSSOP-8
Category Transistors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage N-Ch (abs max) VDS 20 V N-Channel 1
Drain-Source Voltage P-Ch (abs max) VDS -20 V P-Channel 1
Gate-Source Voltage VGS -12 12 V N- and P-Channel 1
Continuous Drain Current N-Ch ID 6.7 A N-Channel, TJ = 150 °C, TC = 25 °C 1
Continuous Drain Current P-Ch ID -6.1 A P-Channel, TJ = 150 °C, TC = 25 °C 1
Continuous Drain Current N-Ch ID 5.7 A N-Channel, TJ = 150 °C, TA = 25 °C (b, c) 1
Continuous Drain Current P-Ch ID -5.1 A P-Channel, TJ = 150 °C, TA = 25 °C (b, c) 1
Pulsed Drain Current N-Ch IDM 30 A N-Channel 1
Pulsed Drain Current P-Ch IDM -30 A P-Channel 1
Max Power Dissipation N-Ch PD 1.6 W N-Channel, TC = 25 °C 1
Max Power Dissipation P-Ch PD 1.7 W P-Channel, TC = 25 °C 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Junction-to-Ambient N-Ch RthJA 85 110 °C/W N-Channel, t ≤ 10 s, surface mounted on 1" x 1" FR4 1
Junction-to-Ambient P-Ch RthJA 81 105 °C/W P-Channel, t ≤ 10 s, surface mounted on 1" x 1" FR4 1
Junction-to-Foot (Drain) N-Ch RthJF 62 80 °C/W N-Channel, steady state 1
Junction-to-Foot (Drain) P-Ch RthJF 57 75 °C/W P-Channel, steady state 1
Drain-Source Breakdown Voltage N-Ch VDS 20 V VGS = 0 V, ID = 250 µA 2
Drain-Source Breakdown Voltage P-Ch VDS -20 V VGS = 0 V, ID = - 250 µA 2
Gate Threshold Voltage N-Ch VGS(th) 0.6 1.5 V VDS = VGS, ID = 250 µA 2
Gate Threshold Voltage P-Ch VGS(th) -0.6 -1.5 V VDS = VGS, ID = - 250 µA 2
Gate-Body Leakage N-Ch IGSS -100 100 nA VDS = 0 V, VGS = ± 12 V 2
Gate-Body Leakage P-Ch IGSS -100 100 nA VDS = 0 V, VGS = ± 12 V 2
Zero Gate Voltage Drain Current N-Ch IDSS 1 µA VDS = 20 V, VGS = 0 V 2
Zero Gate Voltage Drain Current P-Ch IDSS -1 µA VDS = - 20 V, VGS = 0 V 2
Zero Gate Voltage Drain Current N-Ch IDSS 10 µA VDS = 20 V, VGS = 0 V, TJ = 55 °C 2
Zero Gate Voltage Drain Current P-Ch IDSS -10 µA VDS = - 20 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current N-Ch ID(on) 30 A VDS ≥ 5 V, VGS = 4.5 V 2
On-State Drain Current P-Ch ID(on) -30 A VDS ≤ - 5 V, VGS = - 4.5 V 2
Drain-Source On-State Resistance N-Ch RDS(on) 0.018 0.022 Ω VGS = 4.5 V, ID = 5.7 A 2
Drain-Source On-State Resistance P-Ch RDS(on) 0.024 0.03 Ω VGS = - 4.5 V, ID = - 5.1 A 2
Drain-Source On-State Resistance N-Ch RDS(on) 0.029 0.036 Ω VGS = 2.5 V, ID = 4.4 A 2
Drain-Source On-State Resistance P-Ch RDS(on) 0.036 0.045 Ω VGS = - 2.5 V, ID = - 4.2 A 2
Total Gate Charge N-Ch Qg 15 23 nC VDS = 10 V, VGS = 10 V, ID = 5.7 A 2
Total Gate Charge P-Ch Qg 34 51 nC VDS = - 10 V, VGS = - 10 V, ID = - 5.1 A 2
Total Gate Charge N-Ch Qg 6.7 11 nC VDS = 10 V, VGS = 4.5 V, ID = 5.7 A 2
Total Gate Charge P-Ch Qg 17 30 nC VDS = - 10 V, VGS = - 4.5 V, ID = - 5.1 A 2
Turn-On Delay Time N-Ch td(on) 12 20 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 4.5 V, Rg = 1 Ω 3
Turn-On Delay Time P-Ch td(on) 30 45 ns VDD = - 10 V, RL = 2.4 Ω, ID ≅ - 4.1 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Rise Time N-Ch tr 10 15 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 4.5 V, Rg = 1 Ω 3
Rise Time P-Ch tr 25 40 ns VDD = - 10 V, RL = 2.4 Ω, ID ≅ - 4.1 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Turn-Off Delay Time N-Ch td(off) 25 40 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 4.5 V, Rg = 1 Ω 3
Turn-Off Delay Time P-Ch td(off) 45 70 ns VDD = - 10 V, RL = 2.4 Ω, ID ≅ - 4.1 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Fall Time N-Ch tf 10 15 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 4.5 V, Rg = 1 Ω 3
Fall Time P-Ch tf 15 25 ns VDD = - 10 V, RL = 2.4 Ω, ID ≅ - 4.1 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Turn-On Delay Time N-Ch td(on) 10 15 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 10 V, Rg = 1 Ω 3
Turn-On Delay Time P-Ch td(on) 10 15 ns VDD = - 10 V, RL = 2.4 Ω, ID ≅ - 4.1 A, VGEN = - 10 V, Rg = 1 Ω 3
Rise Time P-Ch tr 10 15 ns VDD = - 10 V, RL = 2.4 Ω, ID ≅ - 4.1 A, VGEN = - 10 V, Rg = 1 Ω 3
Turn-Off Delay Time N-Ch td(off) 20 30 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 10 V, Rg = 1 Ω 3
Fall Time N-Ch tf 8 15 ns VDD = 10 V, RL = 2.2 Ω, ID ≅ 4.5 A, VGEN = 10 V, Rg = 1 Ω 3
Body Diode Voltage N-Ch VSD 0.8 1.2 V IS = 4.5 A, VGS = 0 V 3
Body Diode Voltage P-Ch VSD -0.8 -1.2 V IS = - 4.1 A, VGS = 0 V 3
Body Diode Reverse Recovery Time N-Ch trr 15 30 ns IF = 4.5 A, dI/dt = 100 A/µs, TJ = 25 °C 3
Body Diode Reverse Recovery Time P-Ch trr 35 55 ns IF = - 4.1 A, dI/dt = - 100 A/µs, TJ = 25 °C 3
Body Diode Reverse Recovery Charge N-Ch Qrr 6 12 nC IF = 4.5 A, dI/dt = 100 A/µs, TJ = 25 °C 3
Body Diode Reverse Recovery Charge P-Ch Qrr 21 35 nC IF = - 4.1 A, dI/dt = - 100 A/µs, TJ = 25 °C 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper overlies the drain pins. The copper plane connects the drain pins 15

CAD (KiCad official)

  • Symbol: SI6562CDQ-T1-GE3
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: si6562cdq-t1-ge3-etched.step / si6562cdq-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si6562cdq-t1-ge3.step / si6562cdq-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (17 pp, sha256 e07076f9852859cb, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF