component
SI52147-A01AGMR
Public Made by Adomby adom
SILICON LABS Clock Generators / Frequency Synthesizers / PLL, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "si52147-a01agmr",
"version": "0.1.0",
"type": "component",
"description": "SILICON LABS Clock Generators / Frequency Synthesizers / PLL, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"clock and timing",
"si52147-a01agmr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"si52147-a01agmr.kicad_sym",
"si52147-a01agmr.kicad_mod",
"si52147-a01agmr.glb",
"si52147-a01agmr.step",
"si52147-a01agmr.lbr",
"docs/hero.png",
"docs/si52147-a01agmr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"si52147-a01agmr-hero.glb",
"si52147-a01agmr-hero.overlay.json",
"si52147-a01agmr-etched.glb"
],
"component": {
"mpn": "SI52147-A01AGMR",
"manufacturer": "SILICON LABS",
"package": "QFN-48-EP(6x6)",
"pin_count": 49,
"category": "Clock and Timing",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/8c478a5788dc5d00fecb985b74580202.pdf",
"parts": {
"symbol": "si52147-a01agmr.kicad_sym",
"footprint": "si52147-a01agmr.kicad_mod",
"model_3d": "si52147-a01agmr-hero.glb",
"model_3d_plain": "si52147-a01agmr-etched.glb",
"model_3d_step": "si52147-a01agmr-etched.step",
"model_3d_step_plain": "si52147-a01agmr.step",
"lbr": "si52147-a01agmr.lbr"
},
"distributor_links": {
"lcsc": "C970583",
"digikey": "SI52147-A01AGMR-ND",
"mouser": "634-SI52147-A01AGMR"
},
"distributor_check": {
"checked_at": "2026-10-27T00:33:26Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "SI52147-A01AGMR-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "634-SI52147-A01AGMR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "VDD_DIFF",
"type": "power_in",
"description": "3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V)."
},
{
"number": "2",
"name": "VDD_DIFF",
"type": "power_in",
"description": "3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V)."
},
{
"number": "3",
"name": "OE_DIFF0",
"type": "input",
"description": "Active high input pin enables DIFF0, with internal 100 kΩ pull-up."
},
{
"number": "4",
"name": "OE_DIFF1",
"type": "input",
"description": "Active high input pin enables DIFF1, with internal 100 kΩ pull-up."
},
{
"number": "5",
"name": "SSON",
"type": "input",
"description": "Active high input pin enables -0.5% spread on DIFF clocks, with internal 100 kΩ pull-down."
},
{
"number": "6",
"name": "VSS_DIFF",
"type": "power_in",
"description": "Ground."
},
{
"number": "7",
"name": "VSS_DIFF",
"type": "power_in",
"description": "Ground."
},
{
"number": "8",
"name": "OE_DIFF2",
"type": "input",
"description": "Active high input pin enables DIFF2, with internal 100 kΩ pull-up."
},
{
"number": "9",
"name": "OE_DIFF3",
"type": "input",
"description": "Active high input pin enables DIFF3, with internal 100 kΩ pull-up."
},
{
"number": "10",
"name": "OE_DIFF[4:5]",
"type": "input",
"description": "Active high input pin enables DIFF[4:5], with internal 100 kΩ pull-up."
},
{
"number": "11",
"name": "OE_DIFF[6:8]",
"type": "input",
"description": "Active high input pin enables DIFF[6:8], with internal 100 kΩ pull-up."
},
{
"number": "12",
"name": "VDD_DIFF",
"type": "power_in",
"description": "3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V)."
},
{
"number": "13",
"name": "VDD_DIFF",
"type": "power_in",
"description": "3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V)."
},
{
"number": "14",
"name": "DIFF0",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF0 pair)."
},
{
"number": "15",
"name": "DIFF0",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF0 pair)."
},
{
"number": "16",
"name": "VSS_DIFF",
"type": "power_in",
"description": "Ground."
},
{
"number": "17",
"name": "DIFF1",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF1 pair)."
},
{
"number": "18",
"name": "DIFF1",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF1 pair)."
},
{
"number": "19",
"name": "DIFF2",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF2 pair)."
},
{
"number": "20",
"name": "DIFF2",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF2 pair)."
},
{
"number": "21",
"name": "DIFF3",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF3 pair)."
},
{
"number": "22",
"name": "DIFF3",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF3 pair)."
},
{
"number": "23",
"name": "VDD_DIFF",
"type": "power_in",
"description": "3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V)."
},
{
"number": "24",
"name": "VSS_DIFF",
"type": "power_in",
"description": "Ground."
},
{
"number": "25",
"name": "DIFF4",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF4 pair)."
},
{
"number": "26",
"name": "DIFF4",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF4 pair)."
},
{
"number": "27",
"name": "DIFF5",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF5 pair)."
},
{
"number": "28",
"name": "DIFF5",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF5 pair)."
},
{
"number": "29",
"name": "VSS_DIFF",
"type": "power_in",
"description": "Ground."
},
{
"number": "30",
"name": "DIFF6",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF6 pair)."
},
{
"number": "31",
"name": "DIFF6",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF6 pair)."
},
{
"number": "32",
"name": "DIFF7",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF7 pair)."
},
{
"number": "33",
"name": "DIFF7",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF7 pair)."
},
{
"number": "34",
"name": "VDD_DIFF",
"type": "power_in",
"description": "3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V)."
},
{
"number": "35",
"name": "DIFF8",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF8 pair)."
},
{
"number": "36",
"name": "DIFF8",
"type": "output",
"description": "0.7 V, 100 MHz differential clock output (one half of the DIFF8 pair)."
},
{
"number": "37",
"name": "SCLK",
"type": "input",
"description": "I2C compatible SCLOCK input (VIH 2.2 V min, VIL 1.0 V max)."
},
{
"number": "38",
"name": "SDATA",
"type": "bidirectional",
"description": "I2C compatible SDATA input/output (VIH 2.2 V min, VIL 1.0 V max)."
},
{
"number": "39",
"name": "CKPWRGD/PDB",
"type": "input",
"description": "Active low input pin asserts power down (PDB) and disables all outputs, with internal 100 kΩ pull-up; must be driven at all times."
},
{
"number": "40",
"name": "VDD_CORE",
"type": "power_in",
"description": "3.3 V power supply for the core (3.135 to 3.465 V)."
},
{
"number": "41",
"name": "XOUT",
"type": "output",
"description": "25.00 MHz crystal output; float XOUT if using only CLKIN (clock input)."
},
{
"number": "42",
"name": "XIN/CLKIN",
"type": "input",
"description": "25.00 MHz crystal input or 3.3 V, 25 MHz clock input."
},
{
"number": "43",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "44",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "45",
"name": "VSS_CORE",
"type": "power_in",
"description": "Ground."
},
{
"number": "46",
"name": "VSS_DIFF",
"type": "power_in",
"description": "Ground."
},
{
"number": "47",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "48",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "49",
"name": "GND",
"type": "power_in",
"description": "Ground for bottom pad of the IC."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Differential output pairs (DIFF0..DIFF8) are printed with identical names for both pins; the datashe; The pin list on page 17 (diagram text) is ordered differently from Table 7 around pins 5-8 (diagram ; MPN suffix R denotes tape and reel of the same 48-pin QFN; the datasheet gives 6x6 mm body only thro",
"1/49 pins cited to the wrong page (name found elsewhere): ['41:XOUT@p19']"
],
"pages_sent": 25,
"cost_usd": 0.1952,
"at": "2026-10-27T00:30:26"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/8c478a5788dc5d00fecb985b74580202.pdf",
"pages": 25,
"sha256": "9982bf765a362a6e",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "si52147-a01agmr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.02,
6.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "5a550226c4fff52b90b724e5c02deb29a4e01ba01ca0453173ca37f38ff0da37",
"checked": "2026-10-27",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "si52147-a01agmr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.02,
6.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "64c0081b9e7f5ca42a5d9dc39ffe262e82256511dde00c23ec846e210ebd7ef8",
"checked": "2026-10-27",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}