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SI4948BEY-T1-GE3

Vishay Intertech · MOSFETs · SOP-8

SI4948BEY-T1-GE3 from Vishay Intertech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S1	passive	Source terminal of P-channel MOSFET 1, which is rated VDS = -60 V with continuous drain current ID = -3.1 A at TA = 25 °C.
2	G1	passive	Gate of P-channel MOSFET 1, with gate-source voltage limited to ±20 V and gate threshold VGS(th) between -1 V and -3 V.
3	S2	passive	Source terminal of P-channel MOSFET 2, which is rated VDS = -60 V with continuous drain current ID = -3.1 A at TA = 25 °C.
4	G2	passive	Gate of P-channel MOSFET 2, with gate-source voltage limited to ±20 V and gate threshold VGS(th) between -1 V and -3 V.
5	D2	passive	Drain of P-channel MOSFET 2, rated for VDS = -60 V; pin is labelled D2 alongside pin 6.
6	D2	passive	Drain of P-channel MOSFET 2, rated for VDS = -60 V; second drain pin of the same channel.
7	D1	passive	Drain of P-channel MOSFET 1, rated for VDS = -60 V; pin is labelled D1 alongside pin 8.
8	D1	passive	Drain of P-channel MOSFET 1, rated for VDS = -60 V; second drain pin of the same channel.

Key specifications

Parameter	Value
Manufacturer	Vishay Intertech
Package	SOP-8
Category	Transistors/Thyristors
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Gate Threshold Voltage	VGS(th)	-1		-3	V	VDS = VGS, ID = - 250 µA	2
Gate-Body Leakage	IGSS	-100		100	nA	VDS = 0 V, VGS = ± 20 V	2
Zero Gate Voltage Drain Current	IDSS			-1	µA	VDS = - 60 V, VGS = 0 V	2
Zero Gate Voltage Drain Current	IDSS			-10	µA	VDS = - 60 V, VGS = 0 V, TJ = 70 °C	2
On-State Drain Current	ID(on)		-25		A	VDS = - 5 V, VGS = - 10 V	2
Drain-Source On-State Resistance	RDS(on)		0.1	0.12	Ω	VGS = - 10 V, ID = - 3.1 A	2
Drain-Source On-State Resistance	RDS(on)		0.126	0.15	Ω	VGS = - 4.5 V, ID = - 0.2 A	2
Forward Transconductance	gfs		8.5		S	VDS = - 15 V, ID = - 3.1 A	2
Diode Forward Voltage	VSD		-0.8	-1.2	V	IS = - 2 A, VGS = 0 V	2
Total Gate Charge	Qg		14.5	22	nC	VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A	2
Gate-Source Charge	Qgs		2.2		nC	VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A	2
Gate-Drain Charge	Qgd		3.7		nC	VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A	2
Gate Resistance	Rg		14		Ω	f = 1 MHz	2
Turn-On Delay Time	td(on)		10	15	ns	VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω	2
Rise Time	tr		15	22	ns	VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω	2
Turn-Off Delay Time	td(off)		50	75	ns	VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω	2
Fall Time	tf		35	55	ns	VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω	2
Source-Drain Reverse Recovery Time	trr		30	50	ns	IF = - 2 A, dI/dt = 100 A/µs	2
Drain-Source Voltage	VDS	-60			V		1
Gate-Source Voltage	VGS	-20		20	V		1
Continuous Drain Current (TJ = 150 °C), 10 s	ID	-3.1			A	TA = 25 °C	1
Continuous Drain Current (TJ = 150 °C), steady state	ID	-2.4			A	TA = 25 °C	1
Continuous Drain Current (TJ = 150 °C), 10 s	ID	-2.6			A	TA = 70 °C	1
Continuous Drain Current (TJ = 150 °C), steady state	ID	-2			A	TA = 70 °C	1
Pulsed Drain Current (10 µs Pulse Width)	IDM	-25			A	10 µs pulse width	1
Continuous Source Current (Diode Conduction), 10 s	IS	-2			A		1
Continuous Source Current (Diode Conduction), steady state	IS	-1.1			A		1
Avalanche Current	IAS			15	A	L = 0.1 mH	1
Single Pulse Avalanche Energy	EAS			11	mJ		1
Maximum Power Dissipation, 10 s	PD			2.4	W	TA = 25 °C	1
Maximum Power Dissipation, steady state	PD			1.4	W	TA = 25 °C	1
Maximum Power Dissipation, 10 s	PD			1.7	W	TA = 70 °C	1
Maximum Power Dissipation, steady state	PD			0.95	W	TA = 70 °C	1
Operating Junction and Storage Temperature Range	TJ, Tstg	-55		175	°C		1
Maximum Junction-to-Ambient, t ≤ 10 s	RthJA		53	62.5	°C/W	t ≤ 10 s	1
Maximum Junction-to-Ambient, steady state	RthJA		85	110	°C/W	Steady State	1
Maximum Junction-to-Foot, steady state	RthJF		30	37	°C/W	Steady State	1

CAD (KiCad official)

Symbol: SI4948BEY-T1-GE3
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: si4948bey-t1-ge3-etched.step / si4948bey-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4948bey-t1-ge3.step / si4948bey-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Vishay Intertech datasheet (8 pp, sha256 11a8ead95940bc07, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF