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SI4948BEY-T1-E3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SI4948BEY-T1-E3
Vishay Intertech · MOSFETs · SO-8
SI4948BEY-T1-E3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1; gate-source voltage limit is ±20 V. |
| 2 | G1 | input | Gate of P-channel MOSFET 1; VGS maximum ±20 V, threshold -1 to -3 V at ID = -250 µA. |
| 3 | S2 | passive | Source of P-channel MOSFET 2; gate-source voltage limit is ±20 V. |
| 4 | G2 | input | Gate of P-channel MOSFET 2; VGS maximum ±20 V, threshold -1 to -3 V at ID = -250 µA. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, tied with pin 5; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
| 7 | D1 | passive | Drain of P-channel MOSFET 1; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, tied with pin 7; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate Threshold Voltage | VGS(th) | -1 | -3 | V | VDS = VGS, ID = - 250 µA | 2 | |
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = - 60 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -10 | µA | VDS = - 60 V, VGS = 0 V, TJ = 70 °C | 2 | ||
| On-State Drain Current | ID(on) | -25 | A | VDS = - 5 V, VGS = - 10 V | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.1 | 0.12 | Ω | VGS = - 10 V, ID = - 3.1 A | 2 | |
| Drain-Source On-State Resistance | RDS(on) | 0.126 | 0.15 | Ω | VGS = - 4.5 V, ID = - 0.2 A | 2 | |
| Diode Forward Voltage | VSD | -0.8 | -1.2 | V | IS = - 2 A, VGS = 0 V | 2 | |
| Total Gate Charge | Qg | 14.5 | 22 | nC | VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A | 2 | |
| Turn-On Delay Time | td(on) | 10 | 15 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 | |
| Rise Time | tr | 15 | 22 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 50 | 75 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 | |
| Fall Time | tf | 35 | 55 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 | |
| Source-Drain Reverse Recovery Time | trr | 30 | 50 | ns | IF = - 2 A, dI/dt = 100 A/µs | 2 | |
| Drain-Source Voltage | VDS | -60 | V | TA = 25 °C | 1 | ||
| Gate-Source Voltage | VGS | -20 | 20 | V | TA = 25 °C | 1 | |
| Continuous Drain Current, 10 s | ID | -3.1 | A | TJ = 150 °C, TA = 25 °C, 10 s | 1 | ||
| Continuous Drain Current, Steady State | ID | -2.4 | A | TJ = 150 °C, TA = 25 °C, steady state | 1 | ||
| Continuous Drain Current, 10 s | ID | -2.6 | A | TJ = 150 °C, TA = 70 °C, 10 s | 1 | ||
| Continuous Drain Current, Steady State | ID | -2 | A | TJ = 150 °C, TA = 70 °C, steady state | 1 | ||
| Pulsed Drain Current | IDM | -25 | A | 10 µs pulse width | 1 | ||
| Continuous Source Current, 10 s | IS | -2 | A | Diode conduction, 10 s | 1 | ||
| Continuous Source Current, Steady State | IS | -1.1 | A | Diode conduction, steady state | 1 | ||
| Avalanche Current | IAS | 15 | A | L = 0.1 mH | 1 | ||
| Single Pulse Avalanche Energy | EAS | 11 | mJ | L = 0.1 mH | 1 | ||
| Maximum Power Dissipation, 10 s | PD | 2.4 | W | TA = 25 °C, 10 s | 1 | ||
| Maximum Power Dissipation, Steady State | PD | 1.4 | W | TA = 25 °C, steady state | 1 | ||
| Maximum Power Dissipation, 10 s | PD | 1.7 | W | TA = 70 °C, 10 s | 1 | ||
| Maximum Power Dissipation, Steady State | PD | 0.95 | W | TA = 70 °C, steady state | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 175 | °C | 1 | ||
| Junction-to-Ambient Thermal Resistance, t ≤ 10 s | RthJA | 53 | 62.5 | °C/W | t ≤ 10 s, surface mounted 1" x 1" FR4 | 1 | |
| Junction-to-Ambient Thermal Resistance, Steady State | RthJA | 85 | 110 | °C/W | Steady state, surface mounted 1" x 1" FR4 | 1 | |
| Junction-to-Foot Thermal Resistance | RthJF | 30 | 37 | °C/W | Steady state | 1 | |
| Forward Transconductance | gfs | 8.5 | S | VDS = - 15 V, ID = - 3.1 A | 2 | ||
| Gate-Source Charge | Qgs | 2.2 | nC | VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A | 2 | ||
| Gate-Drain Charge | Qgd | 3.7 | nC | VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A | 2 | ||
| Gate Resistance | Rg | 14 | Ω | f = 1 MHz | 2 |
CAD (KiCad official)
- Symbol:
SI4948BEY-T1-E3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
si4948bey-t1-e3-etched.step/si4948bey-t1-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si4948bey-t1-e3.step/si4948bey-t1-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (8 pp, sha256
0ccf3701395e1fd9, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SI4948BEY-T1-E3
**Vishay Intertech** · MOSFETs · SO-8
SI4948BEY-T1-E3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1; gate-source voltage limit is ±20 V. |
| 2 | G1 | input | Gate of P-channel MOSFET 1; VGS maximum ±20 V, threshold -1 to -3 V at ID = -250 µA. |
| 3 | S2 | passive | Source of P-channel MOSFET 2; gate-source voltage limit is ±20 V. |
| 4 | G2 | input | Gate of P-channel MOSFET 2; VGS maximum ±20 V, threshold -1 to -3 V at ID = -250 µA. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, tied with pin 5; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
| 7 | D1 | passive | Drain of P-channel MOSFET 1; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, tied with pin 7; VDS rated -60 V, continuous ID -3.1 A (10 s, TA = 25 °C). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate Threshold Voltage | VGS(th) | -1 | | -3 | V | VDS = VGS, ID = - 250 µA | 2 |
| Gate-Body Leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | µA | VDS = - 60 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -10 | µA | VDS = - 60 V, VGS = 0 V, TJ = 70 °C | 2 |
| On-State Drain Current | ID(on) | -25 | | | A | VDS = - 5 V, VGS = - 10 V | 2 |
| Drain-Source On-State Resistance | RDS(on) | | 0.1 | 0.12 | Ω | VGS = - 10 V, ID = - 3.1 A | 2 |
| Drain-Source On-State Resistance | RDS(on) | | 0.126 | 0.15 | Ω | VGS = - 4.5 V, ID = - 0.2 A | 2 |
| Diode Forward Voltage | VSD | | -0.8 | -1.2 | V | IS = - 2 A, VGS = 0 V | 2 |
| Total Gate Charge | Qg | | 14.5 | 22 | nC | VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A | 2 |
| Turn-On Delay Time | td(on) | | 10 | 15 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 |
| Rise Time | tr | | 15 | 22 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 |
| Turn-Off Delay Time | td(off) | | 50 | 75 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 |
| Fall Time | tf | | 35 | 55 | ns | VDD = - 30 V, RL = 30 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω | 2 |
| Source-Drain Reverse Recovery Time | trr | | 30 | 50 | ns | IF = - 2 A, dI/dt = 100 A/µs | 2 |
| Drain-Source Voltage | VDS | | | -60 | V | TA = 25 °C | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | TA = 25 °C | 1 |
| Continuous Drain Current, 10 s | ID | | | -3.1 | A | TJ = 150 °C, TA = 25 °C, 10 s | 1 |
| Continuous Drain Current, Steady State | ID | | | -2.4 | A | TJ = 150 °C, TA = 25 °C, steady state | 1 |
| Continuous Drain Current, 10 s | ID | | | -2.6 | A | TJ = 150 °C, TA = 70 °C, 10 s | 1 |
| Continuous Drain Current, Steady State | ID | | | -2 | A | TJ = 150 °C, TA = 70 °C, steady state | 1 |
| Pulsed Drain Current | IDM | | | -25 | A | 10 µs pulse width | 1 |
| Continuous Source Current, 10 s | IS | | | -2 | A | Diode conduction, 10 s | 1 |
| Continuous Source Current, Steady State | IS | | | -1.1 | A | Diode conduction, steady state | 1 |
| Avalanche Current | IAS | | | 15 | A | L = 0.1 mH | 1 |
| Single Pulse Avalanche Energy | EAS | | | 11 | mJ | L = 0.1 mH | 1 |
| Maximum Power Dissipation, 10 s | PD | | | 2.4 | W | TA = 25 °C, 10 s | 1 |
| Maximum Power Dissipation, Steady State | PD | | | 1.4 | W | TA = 25 °C, steady state | 1 |
| Maximum Power Dissipation, 10 s | PD | | | 1.7 | W | TA = 70 °C, 10 s | 1 |
| Maximum Power Dissipation, Steady State | PD | | | 0.95 | W | TA = 70 °C, steady state | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 175 | °C | | 1 |
| Junction-to-Ambient Thermal Resistance, t ≤ 10 s | RthJA | | 53 | 62.5 | °C/W | t ≤ 10 s, surface mounted 1" x 1" FR4 | 1 |
| Junction-to-Ambient Thermal Resistance, Steady State | RthJA | | 85 | 110 | °C/W | Steady state, surface mounted 1" x 1" FR4 | 1 |
| Junction-to-Foot Thermal Resistance | RthJF | | 30 | 37 | °C/W | Steady state | 1 |
| Forward Transconductance | gfs | | 8.5 | | S | VDS = - 15 V, ID = - 3.1 A | 2 |
| Gate-Source Charge | Qgs | | 2.2 | | nC | VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A | 2 |
| Gate-Drain Charge | Qgd | | 3.7 | | nC | VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A | 2 |
| Gate Resistance | Rg | | 14 | | Ω | f = 1 MHz | 2 |
## CAD (KiCad official)
- Symbol: `SI4948BEY-T1-E3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `si4948bey-t1-e3-etched.step` / `si4948bey-t1-e3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si4948bey-t1-e3.step` / `si4948bey-t1-e3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](docs/si4948bey-t1-e3-datasheet.pdf) (8 pp, sha256 `0ccf3701395e1fd9`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/si4948bey-t1-e3-datasheet.pdf)