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SI4825DDY-T1-GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SI4825DDY-T1-GE3
Vishay Intertech · MOSFETs · SO-8
SI4825DDY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET, tied with pins 2 and 3; VDS rated -30 V. |
| 2 | S | passive | Source terminal of the P-channel MOSFET, tied with pins 1 and 3; continuous source-drain diode current -4.1 A at TC = 25 °C. |
| 3 | S | passive | Source terminal of the P-channel MOSFET, tied with pins 1 and 2; gate-source voltage limit is ±25 V relative to the gate. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; VGS maximum ±25 V, threshold -1.4 V to -2.5 V at ID = -250 µA. |
| 5 | D | passive | Drain terminal, tied with pins 6, 7 and 8; VDS rated -30 V and continuous drain current -14.9 A at TC = 25 °C. |
| 6 | D | passive | Drain terminal, tied with pins 5, 7 and 8; pulsed drain current up to -60 A. |
| 7 | D | passive | Drain terminal, tied with pins 5, 6 and 8; RDS(on) 0.0125 Ω max at VGS = -10 V. |
| 8 | D | passive | Drain terminal, tied with pins 5, 6 and 7; RDS(on) 0.0205 Ω max at VGS = -4.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SI4825DDY-T1-GE3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
si4825ddy-t1-ge3-etched.step/si4825ddy-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si4825ddy-t1-ge3.step/si4825ddy-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (9 pp, sha256
48fe23d633cdf62a, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SI4825DDY-T1-GE3
**Vishay Intertech** · MOSFETs · SO-8
SI4825DDY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET, tied with pins 2 and 3; VDS rated -30 V. |
| 2 | S | passive | Source terminal of the P-channel MOSFET, tied with pins 1 and 3; continuous source-drain diode current -4.1 A at TC = 25 °C. |
| 3 | S | passive | Source terminal of the P-channel MOSFET, tied with pins 1 and 2; gate-source voltage limit is ±25 V relative to the gate. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; VGS maximum ±25 V, threshold -1.4 V to -2.5 V at ID = -250 µA. |
| 5 | D | passive | Drain terminal, tied with pins 6, 7 and 8; VDS rated -30 V and continuous drain current -14.9 A at TC = 25 °C. |
| 6 | D | passive | Drain terminal, tied with pins 5, 7 and 8; pulsed drain current up to -60 A. |
| 7 | D | passive | Drain terminal, tied with pins 5, 6 and 8; RDS(on) 0.0125 Ω max at VGS = -10 V. |
| 8 | D | passive | Drain terminal, tied with pins 5, 6 and 7; RDS(on) 0.0205 Ω max at VGS = -4.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SI4825DDY-T1-GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `si4825ddy-t1-ge3-etched.step` / `si4825ddy-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si4825ddy-t1-ge3.step` / `si4825ddy-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588879927487291392) (9 pp, sha256 `48fe23d633cdf62a`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/si4825ddy-t1-ge3-datasheet.pdf)