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SI4488DY-T1-E3
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Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSI4488DY-T1-E3
Vishay Intertech · MOSFETs · SO-8
SI4488DY-T1-E3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins (1, 2, 3). |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins (1, 2, 3). |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins (1, 2, 3). |
| 4 | G | input | Gate terminal with a maximum gate-source voltage of ±20 V and RDS(on) specified at VGS = 10 V. |
| 5 | D | passive | Drain terminal, tied to the other drain pins (5, 6, 7, 8), with VDS rated to 150 V. |
| 6 | D | passive | Drain terminal, tied to the other drain pins (5, 6, 7, 8), with VDS rated to 150 V. |
| 7 | D | passive | Drain terminal, tied to the other drain pins (5, 6, 7, 8), with VDS rated to 150 V. |
| 8 | D | passive | Drain terminal, tied to the other drain pins (5, 6, 7, 8), with VDS rated to 150 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate Threshold Voltage | VGS(th) | 2 | V | VDS = VGS, ID = 250 µA | 2 | ||
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 120 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current (55 °C) | IDSS | 5 | µA | VDS = 120 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current | ID(on) | 50 | A | VDS ≥ 5 V, VGS = 10 V | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.041 | 0.05 | Ω | VGS = 10 V, ID = 5 A | 2 | |
| Diode Forward Voltage | VSD | 0.75 | 1.1 | V | IS = 2.8 A, VGS = 0 V | 2 | |
| Total Gate Charge | Qg | 30 | 36 | nC | VDS = 75 V, VGS = 10 V, ID = 5 A | 2 | |
| Gate Resistance | Rg | 0.2 | 0.85 | 1.2 | Ω | 2 | |
| Turn-On Delay Time | td(on) | 12 | 18 | ns | VDD = 75 V, RL = 15 Ω, ID ≅ 5 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Rise Time | tr | 7 | 11 | ns | VDD = 75 V, RL = 15 Ω, ID ≅ 5 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 22 | 33 | ns | VDD = 75 V, RL = 15 Ω, ID ≅ 5 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Fall Time | tf | 10 | 15 | ns | VDD = 75 V, RL = 15 Ω, ID ≅ 5 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Source-Drain Reverse Recovery Time | trr | 40 | 70 | ns | IF = 2.8 A, dI/dt = 100 A/µs | 2 | |
| Forward Transconductance | gfs | 18 | S | VDS = 15 V, ID = 5 A | 2 | ||
| Gate-Source Charge | Qgs | 8.5 | nC | VDS = 75 V, VGS = 10 V, ID = 5 A | 2 | ||
| Gate-Drain Charge | Qgd | 8.5 | nC | VDS = 75 V, VGS = 10 V, ID = 5 A | 2 | ||
| Drain-Source Voltage | VDS | 150 | V | TA = 25 °C | 1 | ||
| Gate-Source Voltage | VGS | -20 | 20 | V | TA = 25 °C | 1 | |
| Continuous Drain Current, 10 s | ID | 5 | A | TJ = 150 °C, TA = 25 °C, 10 s | 1 | ||
| Continuous Drain Current, Steady State | ID | 3.5 | A | TJ = 150 °C, TA = 25 °C | 1 | ||
| Continuous Drain Current, 10 s | ID | 4 | A | TJ = 150 °C, TA = 70 °C, 10 s | 1 | ||
| Continuous Drain Current, Steady State | ID | 2.8 | A | TJ = 150 °C, TA = 70 °C | 1 | ||
| Pulsed Drain Current | IDM | 50 | A | 1 | |||
| Avalanche Current | IAS | 25 | A | L = 0.1 mH | 1 | ||
| Continuous Source Current, 10 s | IS | 2.8 | A | Diode conduction, 10 s | 1 | ||
| Continuous Source Current, Steady State | IS | 1.4 | A | Diode conduction | 1 | ||
| Maximum Power Dissipation, 10 s | PD | 3.1 | W | TA = 25 °C, 10 s | 1 | ||
| Maximum Power Dissipation, Steady State | PD | 1.56 | W | TA = 25 °C | 1 | ||
| Maximum Power Dissipation, 10 s | PD | 2 | W | TA = 70 °C, 10 s | 1 | ||
| Maximum Power Dissipation, Steady State | PD | 1 | W | TA = 70 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Junction-to-Ambient Thermal Resistance, t ≤ 10 s | RthJA | 33 | 40 | °C/W | t ≤ 10 s | 1 | |
| Junction-to-Ambient Thermal Resistance, Steady State | RthJA | 65 | 80 | °C/W | Steady State | 1 | |
| Junction-to-Foot (Drain) Thermal Resistance | RthJF | 17 | 21 | °C/W | Steady State | 1 |
CAD (KiCad official)
- Symbol:
SI4488DY-T1-E3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
si4488dy-t1-e3-etched.step/si4488dy-t1-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si4488dy-t1-e3.step/si4488dy-t1-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (8 pp, sha256
c806ae42116b0f3f, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).