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SI4461-C2A-GMR

Public Made by Adom

by adom

SILICON LABS RF Transceiver ICs, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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SI4461-C2A-GMR

SILICON LABS · RF Transceiver ICs · QFN-20-EP(4x4)

SI4461-C2A-GMR from SILICON LABS, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDN input Shutdown input, 0-VDD V digital; must be 0 in all modes except Shutdown, and when 1 the chip is completely shut down and register contents are lost.
2 RXp input Differential RF input of the LNA; see application schematic for example matching network.
3 RXn input Differential RF input of the LNA; see application schematic for example matching network.
4 TX output Transmit output; PA output is open-drain so the L-C match must supply VDD (+3.3 VDC nominal) to this pin.
5 NC unconnected Not connected internally to any circuitry; recommended to connect to GND per the reference design schematic.
6 VDD power_in +1.8 to +3.8 V supply input to internal regulators; recommended +3.3 V.
7 TXRAMP output Programmable bias output with ramp capability for external FET PA.
8 VDD power_in +1.8 to +3.8 V supply input to internal regulators; recommended +3.3 V.
9 GPIO0 bidirectional General purpose digital I/O configurable via registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
10 GPIO1 bidirectional General purpose digital I/O configurable via registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
11 nIRQ output Interrupt status output, set low on any interrupt event; no external pull-up required but may be desirable if multiple interrupt lines are connected.
12 SCLK input Serial clock input, 0-VDD V digital, for the 4-line serial bus; data is clocked in on positive edge transitions.
13 SDO output 0-VDD V digital output providing serial readback of the internal control registers.
14 SDI input Serial data input, 0-VDD V digital, for the 4-line serial bus.
15 nSEL input Serial interface select input, 0-VDD V digital, providing select/enable for the 4-line serial bus.
16 XOUT output Crystal oscillator output; connect to an external 25 to 32 MHz crystal, or leave floating when driving an external source on XIN.
17 XIN input Crystal oscillator input; connect to an external 25 to 32 MHz crystal or to an external source.
18 GND power_in Leave floating when using an XTAL per the reference design; when using a TCXO connect to TCXO GND, separate from the board reference ground plane.
19 GPIO2 bidirectional General purpose digital I/O configurable via registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
20 GPIO3 bidirectional General purpose digital I/O configurable via registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
21 PADDLE_GND power_in Exposed paddle supplying RF and circuit ground for the entire chip; requires a good solder connection to the PCB ground plane.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-20-EP(4x4)
Category RF & Radio
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VDD 1.8 3.3 3.8 V 4
Shutdown current IShutdown 30 1300 nA RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF 4
Standby current IStandby 40 2900 nA Register values maintained and RC oscillator/WUT OFF 4
Sleep current (RC oscillator) ISleepRC 740 3800 nA RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF 4
RX mode current, high performance IRXH 13.7 22 mA High Performance Mode (measured at 915 MHz and 40 kbps data rate) 4
TX mode current (Si4461) +16 dBm ITX_+16 43 55 mA +16 dBm output power, class-E match, 868 MHz, 3.3 V 4
TX mode current (Si4461) +13 dBm ITX_+13 33.5 40 mA +13 dBm output power, switched-current match, 868 MHz, 3.3 V 4
Synthesizer frequency range 850-1050 FSYN 850 1050 MHz 5
Synthesizer frequency range 350-525 FSYN 350 525 MHz 5
Synthesizer frequency range 284-350 FSYN 284 350 MHz 5
Synthesizer frequency range 142-175 FSYN 142 175 MHz 5
Phase noise 10 kHz, 169 MHz L(fM) -117 -108 dBc/Hz F = 10 kHz, 169 MHz, High Perf Mode 5
Phase noise 100 kHz, 169 MHz L(fM) -120 -115 dBc/Hz F = 100 kHz, 169 MHz, High Perf Mode 5
Phase noise 1 MHz, 169 MHz L(fM) -138 -135 dBc/Hz F = 1 MHz, 169 MHz, High Perf Mode 5
Phase noise 10 MHz, 169 MHz L(fM) -148 -143 dBc/Hz F = 10 MHz, 169 MHz, High Perf Mode 5
Phase noise 10 kHz, 915 MHz L(fM) -102 -94 dBc/Hz F = 10 kHz, 915 MHz, High Perf Mode 5
Phase noise 100 kHz, 915 MHz L(fM) -105 -97 dBc/Hz F = 100 kHz, 915 MHz, High Perf Mode 5
Phase noise 1 MHz, 915 MHz L(fM) -125 -122 dBc/Hz F = 1 MHz, 915 MHz, High Perf Mode 5
Phase noise 10 MHz, 915 MHz L(fM) -138 -135 dBc/Hz F = 10 MHz, 915 MHz, High Perf Mode 5
RX sensitivity 40 kbps, 169 MHz PRX_40 -110 -108 dBm BER < 0.1%, 40 kbps, GFSK, BT = 0.5, Δf = 20 kHz 6
RX sensitivity 100 kbps, 169 MHz PRX_100 -106 -104 dBm BER < 0.1%, 100 kbps, GFSK, BT = 0.5, Δf = 50 kHz 6
RX sensitivity 500 kbps, 169 MHz PRX_500 -98 -96 dBm BER < 0.1%, 500 kbps, GFSK, BT = 0.5, Δf = 250 kHz 6
RX sensitivity 40 kbps, 915/868 MHz PRX_40 -109 -107 dBm BER < 0.1%, 40 kbps, GFSK, BT = 0.5, Δf = 20 kHz 7
RX sensitivity 100 kbps, 915/868 MHz PRX_100 -104 -102 dBm BER < 0.1%, 100 kbps, GFSK, BT = 0.5, Δf = 50 kHz 7
RX sensitivity 500 kbps, 915/868 MHz PRX_500 -97 -92 dBm BER < 0.1%, 500 kbps, GFSK, BT = 0.5, Δf = 250 kHz 7
RX channel bandwidth BW 1.1 850 kHz 7
1-Ch offset selectivity, 169 MHz C/I1-CH -69 -59 dB channel spacing = 12.5 kHz, RX channel BW = 4.8 kHz 7
1-Ch offset selectivity, 450 MHz C/I1-CH -60 -50 dB channel spacing = 12.5 kHz, RX channel BW = 4.8 kHz 7
1-Ch offset selectivity, 868/915 MHz C/I1-CH -55 -45 dB channel spacing = 12.5 kHz, RX channel BW = 4.8 kHz 7
Blocking 1 MHz offset 1MBLOCK -79 -68 dB RX channel BW = 4.8 kHz 7
Blocking 8 MHz offset 8MBLOCK -86 -75 dB RX channel BW = 4.8 kHz 7
Image rejection, no calibration, 460 MHz ImREJ 30 40 dB No image rejection calibration, RF = 460 MHz 8
Image rejection, calibrated, 460 MHz ImREJ 40 55 dB With image rejection calibration, RF = 460 MHz 8
Image rejection, no calibration, 915 MHz ImREJ 30 45 dB No image rejection calibration, RF = 915 MHz 8
Image rejection, calibrated, 915 MHz ImREJ 40 52 dB With image rejection calibration, RF = 915 MHz 8
Image rejection, no calibration, 169 MHz ImREJ 35 45 dB No image rejection calibration, RF = 169 MHz 8
Image rejection, calibrated, 169 MHz ImREJ 45 60 dB With image rejection calibration, RF = 169 MHz 8
(G)FSK data rate DRFSK 0.1 500 kbps 9
4(G)FSK data rate DR4FSK 0.2 1000 kbps 9
OOK data rate DROOK 0.1 120 kbps 9
Output power range (Si4461) PTX61 -40 16 dBm Typical range at 3.3 V with Class E Match optimized for best PA efficiency 9
TX RF output steps PRF_OUT 0.25 0.4 dB Using switched current match within 6 dB of max power using CLE match within 6 dB of max power 10
TX RF output level variation vs. temperature PRF_TEMP 2.3 3 dB -40 to +85 C 10
TX RF output level variation vs. frequency PRF_FREQ 0.6 1.7 dB Measured across 902-928 MHz 10
XTAL range XTALRange 25 32 MHz 11
POR reset time tPOR 6 ms 11
Input current IIN -1 1 µA 0<VIN< VDD 12
Input current if pullup is activated IINP 1 4 µA VIL = 0 V 12
Operating ambient temperature range TA -40 85 °C 13
Junction temperature maximum Tj 105 °C Based on RF evaluation board measurements 13
Storage temperature range TSTG -55 150 °C 13
VDD to GND VDD -0.3 3.8 V 13
Instantaneous VRF-peak to GND on TX output pin VRF-peak -0.3 8 V 13
Sustained VRF-peak to GND on TX output pin VRF-peak -0.3 6.5 V 13
Voltage on analog inputs -0.7 3.8 V -0.7 to VDD + 0.3 V; max shown at VDD = 3.8 V 13
RX input power 10 dBm 13
Thermal impedance junction to ambient θJA 25 °C/w Based on RF evaluation board measurements 13

CAD (KiCad official)

  • Symbol: SI4461-C2A-GMR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: si4461-c2a-gmr-etched.step / si4461-c2a-gmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4461-c2a-gmr.step / si4461-c2a-gmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (53 pp, sha256 8882300b5eda9509, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF