SI4460-C2A-GMR

SKYWORKS SILICON LABS · RF Transceiver ICs · QFN-20-EP(4x4)

SI4460-C2A-GMR from SKYWORKS SILICON LABS, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDN	input	Shutdown input (0-VDD V digital); it must be 0 in all modes except shutdown, and when it is 1 the chip is fully shut down and register contents are lost.
2	RXp	input	Differential RF input pin of the LNA; see the application schematic for the example matching network.
3	RXn	input	Differential RF input pin of the LNA; see the application schematic for the example matching network.
4	TX	output	Transmit output; the PA output is open-drain, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin.
5	NC	unconnected	Not connected internally to any circuitry; the datasheet recommends connecting this pin to GND per the reference design schematic.
6	VDD	power_in	Supply voltage input to the internal regulators, +1.8 to +3.8 V; the recommended supply voltage is +3.3 V.
7	TXRAMP	output	Programmable bias output with ramp capability for an external FET PA; see section 5.4 Transmitter (TX).
8	VDD	power_in	Supply voltage input to the internal regulators, +1.8 to +3.8 V; the recommended supply voltage is +3.3 V.
9	GPIO0	bidirectional	General-purpose digital I/O (0-VDD V) configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
10	GPIO1	bidirectional	General-purpose digital I/O configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
11	nIRQ	output	General microcontroller interrupt status output that is set low when an interrupt event occurs; no external pull-up is required but one may be desirable if multiple interrupt lines are connected.
12	SCLK	input	Serial clock input for the 4-line serial data bus (0-VDD V digital); data is clocked into the device on positive edge transitions.
13	SDO	output	Serial readback output (0-VDD V digital) that provides readback of the internal control registers.
14	SDI	input	Serial data input (0-VDD V digital) providing the serial data stream for the 4-line serial data bus.
15	nSEL	input	Serial interface select input (0-VDD V digital) providing the select/enable function for the 4-line serial data bus.
16	XOUT	output	Crystal oscillator output; connect to an external 25 to 32 MHz crystal, or leave floating when driving the device with an external source on XIN.
17	XIN	input	Crystal oscillator input; connect to an external 25 to 32 MHz crystal or to an external reference source.
18	GND	power_in	Ground; when using a crystal leave floating per the reference design, and when using a TCXO connect to TCXO GND, which should be separate from the board's reference ground plane.
19	GPIO2	bidirectional	General-purpose digital I/O configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
20	GPIO3	bidirectional	General-purpose digital I/O configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
21	PADDLE_GND	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	SKYWORKS SILICON LABS
Package	QFN-20-EP(4x4)
Category	RF And Wireless
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage Range	VDD	1.8	3.3	3.8	V		4
Shutdown Current	IShutdown		30	1300	nA	RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF	4
Standby Current	IStandby		40	2900	nA	Register values maintained and RC oscillator/WUT OFF	4
Sleep Current (RC)	ISleepRC		740	3800	nA	RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF	4
RX Mode Current (High Performance Mode)	IRXH		13.7	22	mA	High Performance Mode (measured at 915 MHz and 40 kbps data rate)	4
Synthesizer Frequency Range 850-1050 MHz	FSYN	850		1050	MHz		5
Synthesizer Frequency Range 350-525 MHz	FSYN	350		525	MHz		5
Synthesizer Frequency Range 284-350 MHz	FSYN	284		350	MHz		5
Synthesizer Frequency Range 142-175 MHz	FSYN	142		175	MHz		5
Phase Noise 10 kHz offset	L(fM)		-102	-94	dBc/Hz	F = 10 kHz, 915 MHz, High Perf Mode	5
Phase Noise 100 kHz offset	L(fM)		-105	-97	dBc/Hz	F = 100 kHz, 915 MHz, High Perf Mode	5
Phase Noise 1 MHz offset	L(fM)		-125	-122	dBc/Hz	F = 1 MHz, 915 MHz, High Perf Mode	5
Phase Noise 10 MHz offset	L(fM)		-138	-135	dBc/Hz	F = 10 MHz, 915 MHz, High Perf Mode	5
RX Sensitivity 915/868 MHz 0.5 kbps (PRX_40 row, 40 kbps)	PRX_40		-109	-107	dBm	BER < 0.1%, 40 kbps, GFSK, BT = 0.5, f= 20 kHz	7
RX Sensitivity 915/868 MHz (PRX_100)	PRX_100		-104	-102	dBm	BER < 0.1%, 100 kbps, GFSK, BT = 0.5, f= 50 kHz	7
RX Sensitivity 915/868 MHz (PRX_500)	PRX_500		-97	-92	dBm	BER < 0.1%, 500 kbps, GFSK, BT = 0.5, f= 250 kHz	7
RX Sensitivity 915/868 MHz OOK 4.8 kbps	PRX_OOK		-108	-104	dBm	BER < 0.1%, 4.8 kbps, 350 kHz BW, OOK, PN15 data	7
RX Sensitivity 915/868 MHz OOK 40 kbps	PRX_OOK		-101	-97	dBm	BER < 0.1%, 40 kbps, 350 kHz BW, OOK, PN15 data	7
RX Sensitivity 915/868 MHz OOK 120 kbps	PRX_OOK		-96	-91	dBm	BER < 0.1%, 120 kbps, 350 kHz BW, OOK, PN15 data	7
RX Channel Bandwidth	BW	1.1		850	kHz		7
1-Ch Offset Selectivity 868/915 MHz	C/I1-CH		-55	-45	dB	Desired ref signal 3 dB above sensitivity, BER < 0.1%; interferer CW; desired 2.4 kbps F = 1.2 kHz GFSK BT = 0.5; RX channel BW = 4.8 kHz; channel spacing = 12.5 kHz	7
Blocking 1 MHz Offset	1MBLOCK		-79	-68	dB	Desired ref signal 3 dB above sensitivity, BER = 0.1%; interferer CW; desired 2.4 kbps F = 1.2 kHz GFSK BT = 0.5; RX channel BW = 4.8 kHz	7
Blocking 8 MHz Offset	8MBLOCK		-86	-75	dB		7
Image Rejection (no calibration) 915 MHz	ImREJ	30	45		dB	No image rejection calibration; rejection at image frequency; RF = 915 MHz; IF = 468.75 kHz	8
Image Rejection (with calibration) 915 MHz	ImREJ	40	52		dB	With image rejection calibration in Si446x; rejection at image frequency; RF = 915 MHz; IF = 468.75 kHz	8
(G)FSK Data Rate	DRFSK	0.1		500	kbps		9
4(G)FSK Data Rate	DR4FSK	0.2		1000	kbps		9
OOK Data Rate	DROOK	0.1		120	kbps		9
Output Power Range (Si4460)	PTX60	-20		12.5	dBm	Typical range at 3.3 V with Class E match optimized for best PA efficiency	9
Output Power Variation (Si4460) 915 MHz		9	10	11	dBm	At 10 dBm PA power setting, 915 MHz, Class E match, 3.3 V, 25 °C	10
Output Power Variation (Si4460) 169 MHz		9.5	10	10.5	dBm	At 10 dBm PA power setting, 169 MHz, Square Wave match, 3.3 V, 25 °C	10
TX RF Output Steps	PRF_OUT		0.25	0.4	dB	Using switched current match within 6 dB of max power using CLE match within 6 dB of max power	10
TX RF Output Level Variation vs Temperature	PRF_TEMP		2.3	3	dB	-40 to +85 C	10
TX RF Output Level Variation vs Frequency	PRF_FREQ		0.6	1.7	dB	Measured across 902-928 MHz	10
Microcontroller Clock Output Frequency Range (lower limit)	FMC	32.768			kHz	Configurable to Fxtal or Fxtal divided by 2, 3, 7.5, 10, 15, or 30; 32.768 kHz also supported	11
XTAL Range	XTALRange	25		32	MHz	Tested using external clock source (similar to TCXO)	11
POR Reset Time	tPOR			6	ms		11
Input Current	IIN	-1		1	µA	0<VIN<VDD	12
Input Current If Pullup is Activated	IINP	1		4	µA	VIL = 0 V	12
Operating Ambient Temperature Range	TA	-40		85	°C		13
Thermal Impedance Junction to Ambient	θJA		25		°C/W	Based on RF evaluation board measurements	13
Junction Temperature Maximum Value	Tj			105	°C		13
Storage Temperature Range	TSTG	-55		150	°C		13
VDD to GND	VDD	-0.3		3.8	V		13
Instantaneous VRF-peak to GND on TX Output Pin	VRF-peak	-0.3		8	V	Instantaneous	13
Sustained VRF-peak to GND on TX Output Pin	VRF-peak	-0.3		6.5	V	Sustained	13
Voltage on Analog Inputs (lower limit)		-0.7			V		13
RX Input Power				10	dBm		13

CAD (KiCad official)

Symbol: SI4460-C2A-GMR
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
3D model files: si4460-c2a-gmr-etched.step / si4460-c2a-gmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4460-c2a-gmr.step / si4460-c2a-gmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SKYWORKS SILICON LABS datasheet (53 pp, sha256 8882300b5eda9509, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# SI4460-C2A-GMR

**SKYWORKS SILICON LABS** · RF Transceiver ICs · QFN-20-EP(4x4)

SI4460-C2A-GMR from SKYWORKS SILICON LABS, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDN | input | Shutdown input (0-VDD V digital); it must be 0 in all modes except shutdown, and when it is 1 the chip is fully shut down and register contents are lost. |
| 2 | RXp | input | Differential RF input pin of the LNA; see the application schematic for the example matching network. |
| 3 | RXn | input | Differential RF input pin of the LNA; see the application schematic for the example matching network. |
| 4 | TX | output | Transmit output; the PA output is open-drain, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. |
| 5 | NC | unconnected | Not connected internally to any circuitry; the datasheet recommends connecting this pin to GND per the reference design schematic. |
| 6 | VDD | power_in | Supply voltage input to the internal regulators, +1.8 to +3.8 V; the recommended supply voltage is +3.3 V. |
| 7 | TXRAMP | output | Programmable bias output with ramp capability for an external FET PA; see section 5.4 Transmitter (TX). |
| 8 | VDD | power_in | Supply voltage input to the internal regulators, +1.8 to +3.8 V; the recommended supply voltage is +3.3 V. |
| 9 | GPIO0 | bidirectional | General-purpose digital I/O (0-VDD V) configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control. |
| 10 | GPIO1 | bidirectional | General-purpose digital I/O configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control. |
| 11 | nIRQ | output | General microcontroller interrupt status output that is set low when an interrupt event occurs; no external pull-up is required but one may be desirable if multiple interrupt lines are connected. |
| 12 | SCLK | input | Serial clock input for the 4-line serial data bus (0-VDD V digital); data is clocked into the device on positive edge transitions. |
| 13 | SDO | output | Serial readback output (0-VDD V digital) that provides readback of the internal control registers. |
| 14 | SDI | input | Serial data input (0-VDD V digital) providing the serial data stream for the 4-line serial data bus. |
| 15 | nSEL | input | Serial interface select input (0-VDD V digital) providing the select/enable function for the 4-line serial data bus. |
| 16 | XOUT | output | Crystal oscillator output; connect to an external 25 to 32 MHz crystal, or leave floating when driving the device with an external source on XIN. |
| 17 | XIN | input | Crystal oscillator input; connect to an external 25 to 32 MHz crystal or to an external reference source. |
| 18 | GND | power_in | Ground; when using a crystal leave floating per the reference design, and when using a TCXO connect to TCXO GND, which should be separate from the board's reference ground plane. |
| 19 | GPIO2 | bidirectional | General-purpose digital I/O configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control. |
| 20 | GPIO3 | bidirectional | General-purpose digital I/O configurable through registers for functions such as microcontroller clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control. |
| 21 | PADDLE_GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS SILICON LABS |
| Package | QFN-20-EP(4x4) |
| Category | RF And Wireless |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage Range | VDD | 1.8 | 3.3 | 3.8 | V |  | 4 |
| Shutdown Current | IShutdown |  | 30 | 1300 | nA | RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF | 4 |
| Standby Current | IStandby |  | 40 | 2900 | nA | Register values maintained and RC oscillator/WUT OFF | 4 |
| Sleep Current (RC) | ISleepRC |  | 740 | 3800 | nA | RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF | 4 |
| RX Mode Current (High Performance Mode) | IRXH |  | 13.7 | 22 | mA | High Performance Mode (measured at 915 MHz and 40 kbps data rate) | 4 |
| Synthesizer Frequency Range 850-1050 MHz | FSYN | 850 |  | 1050 | MHz |  | 5 |
| Synthesizer Frequency Range 350-525 MHz | FSYN | 350 |  | 525 | MHz |  | 5 |
| Synthesizer Frequency Range 284-350 MHz | FSYN | 284 |  | 350 | MHz |  | 5 |
| Synthesizer Frequency Range 142-175 MHz | FSYN | 142 |  | 175 | MHz |  | 5 |
| Phase Noise 10 kHz offset | L(fM) |  | -102 | -94 | dBc/Hz | F = 10 kHz, 915 MHz, High Perf Mode | 5 |
| Phase Noise 100 kHz offset | L(fM) |  | -105 | -97 | dBc/Hz | F = 100 kHz, 915 MHz, High Perf Mode | 5 |
| Phase Noise 1 MHz offset | L(fM) |  | -125 | -122 | dBc/Hz | F = 1 MHz, 915 MHz, High Perf Mode | 5 |
| Phase Noise 10 MHz offset | L(fM) |  | -138 | -135 | dBc/Hz | F = 10 MHz, 915 MHz, High Perf Mode | 5 |
| RX Sensitivity 915/868 MHz 0.5 kbps (PRX_40 row, 40 kbps) | PRX_40 |  | -109 | -107 | dBm | BER < 0.1%, 40 kbps, GFSK, BT = 0.5, f= 20 kHz | 7 |
| RX Sensitivity 915/868 MHz (PRX_100) | PRX_100 |  | -104 | -102 | dBm | BER < 0.1%, 100 kbps, GFSK, BT = 0.5, f= 50 kHz | 7 |
| RX Sensitivity 915/868 MHz (PRX_500) | PRX_500 |  | -97 | -92 | dBm | BER < 0.1%, 500 kbps, GFSK, BT = 0.5, f= 250 kHz | 7 |
| RX Sensitivity 915/868 MHz OOK 4.8 kbps | PRX_OOK |  | -108 | -104 | dBm | BER < 0.1%, 4.8 kbps, 350 kHz BW, OOK, PN15 data | 7 |
| RX Sensitivity 915/868 MHz OOK 40 kbps | PRX_OOK |  | -101 | -97 | dBm | BER < 0.1%, 40 kbps, 350 kHz BW, OOK, PN15 data | 7 |
| RX Sensitivity 915/868 MHz OOK 120 kbps | PRX_OOK |  | -96 | -91 | dBm | BER < 0.1%, 120 kbps, 350 kHz BW, OOK, PN15 data | 7 |
| RX Channel Bandwidth | BW | 1.1 |  | 850 | kHz |  | 7 |
| 1-Ch Offset Selectivity 868/915 MHz | C/I1-CH |  | -55 | -45 | dB | Desired ref signal 3 dB above sensitivity, BER < 0.1%; interferer CW; desired 2.4 kbps F = 1.2 kHz GFSK BT = 0.5; RX channel BW = 4.8 kHz; channel spacing = 12.5 kHz | 7 |
| Blocking 1 MHz Offset | 1MBLOCK |  | -79 | -68 | dB | Desired ref signal 3 dB above sensitivity, BER = 0.1%; interferer CW; desired 2.4 kbps F = 1.2 kHz GFSK BT = 0.5; RX channel BW = 4.8 kHz | 7 |
| Blocking 8 MHz Offset | 8MBLOCK |  | -86 | -75 | dB |  | 7 |
| Image Rejection (no calibration) 915 MHz | ImREJ | 30 | 45 |  | dB | No image rejection calibration; rejection at image frequency; RF = 915 MHz; IF = 468.75 kHz | 8 |
| Image Rejection (with calibration) 915 MHz | ImREJ | 40 | 52 |  | dB | With image rejection calibration in Si446x; rejection at image frequency; RF = 915 MHz; IF = 468.75 kHz | 8 |
| (G)FSK Data Rate | DRFSK | 0.1 |  | 500 | kbps |  | 9 |
| 4(G)FSK Data Rate | DR4FSK | 0.2 |  | 1000 | kbps |  | 9 |
| OOK Data Rate | DROOK | 0.1 |  | 120 | kbps |  | 9 |
| Output Power Range (Si4460) | PTX60 | -20 |  | 12.5 | dBm | Typical range at 3.3 V with Class E match optimized for best PA efficiency | 9 |
| Output Power Variation (Si4460) 915 MHz |  | 9 | 10 | 11 | dBm | At 10 dBm PA power setting, 915 MHz, Class E match, 3.3 V, 25 °C | 10 |
| Output Power Variation (Si4460) 169 MHz |  | 9.5 | 10 | 10.5 | dBm | At 10 dBm PA power setting, 169 MHz, Square Wave match, 3.3 V, 25 °C | 10 |
| TX RF Output Steps | PRF_OUT |  | 0.25 | 0.4 | dB | Using switched current match within 6 dB of max power using CLE match within 6 dB of max power | 10 |
| TX RF Output Level Variation vs Temperature | PRF_TEMP |  | 2.3 | 3 | dB | -40 to +85 C | 10 |
| TX RF Output Level Variation vs Frequency | PRF_FREQ |  | 0.6 | 1.7 | dB | Measured across 902-928 MHz | 10 |
| Microcontroller Clock Output Frequency Range (lower limit) | FMC | 32.768 |  |  | kHz | Configurable to Fxtal or Fxtal divided by 2, 3, 7.5, 10, 15, or 30; 32.768 kHz also supported | 11 |
| XTAL Range | XTALRange | 25 |  | 32 | MHz | Tested using external clock source (similar to TCXO) | 11 |
| POR Reset Time | tPOR |  |  | 6 | ms |  | 11 |
| Input Current | IIN | -1 |  | 1 | µA | 0<VIN<VDD | 12 |
| Input Current If Pullup is Activated | IINP | 1 |  | 4 | µA | VIL = 0 V | 12 |
| Operating Ambient Temperature Range | TA | -40 |  | 85 | °C |  | 13 |
| Thermal Impedance Junction to Ambient | θJA |  | 25 |  | °C/W | Based on RF evaluation board measurements | 13 |
| Junction Temperature Maximum Value | Tj |  |  | 105 | °C |  | 13 |
| Storage Temperature Range | TSTG | -55 |  | 150 | °C |  | 13 |
| VDD to GND | VDD | -0.3 |  | 3.8 | V |  | 13 |
| Instantaneous VRF-peak to GND on TX Output Pin | VRF-peak | -0.3 |  | 8 | V | Instantaneous | 13 |
| Sustained VRF-peak to GND on TX Output Pin | VRF-peak | -0.3 |  | 6.5 | V | Sustained | 13 |
| Voltage on Analog Inputs (lower limit) |  | -0.7 |  |  | V |  | 13 |
| RX Input Power |  |  |  | 10 | dBm |  | 13 |

## CAD (KiCad official)

- Symbol: `SI4460-C2A-GMR`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`
- 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `si4460-c2a-gmr-etched.step` / `si4460-c2a-gmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si4460-c2a-gmr.step` / `si4460-c2a-gmr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [SKYWORKS SILICON LABS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588895788924096512) (53 pp, sha256 `8882300b5eda9509`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/si4460-c2a-gmr-datasheet.pdf)