component

SI4447ADY-T1-GE3

Public Made by Adom

by adom

Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorssi4447ady-t1-ge3factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers si4447ady-t1-ge3: viewers · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3-etched.glb Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3-etched.step si4447ady-t1-ge3: factory component page (tier=lcsc) · Ray 17d ago
si4447ady-t1-ge3-hero.glb si4447ady-t1-ge3: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
si4447ady-t1-ge3-hero.overlay.json Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3.glb Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3.kicad_mod Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3.kicad_sym Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3.lbr Publish 0.1.0 · Ray 17d ago
si4447ady-t1-ge3.step Publish 0.1.0 · Ray 17d ago

SI4447ADY-T1-GE3

Vishay Intertech · MOSFETs · SO-8

SI4447ADY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the P-channel MOSFET; absolute maximum drain-source voltage is -40 V and continuous drain current is -7.2 A (TC = 25 °C).
2 S passive Source terminal of the P-channel MOSFET, one of three source pins tied to the source of the device; absolute maximum drain-source voltage is -40 V.
3 S passive Source terminal of the P-channel MOSFET, one of three source pins tied to the source of the device; absolute maximum drain-source voltage is -40 V.
4 G input Gate terminal of the P-channel MOSFET; gate-source voltage is rated ±20 V per the absolute maximum ratings.
5 D passive Drain terminal of the P-channel MOSFET; absolute maximum drain-source voltage is -40 V.
6 D passive Drain terminal of the P-channel MOSFET, one of four drain pins tied to the drain of the device; absolute maximum drain-source voltage is -40 V.
7 D passive Drain terminal of the P-channel MOSFET, one of four drain pins tied to the drain of the device; absolute maximum drain-source voltage is -40 V.
8 D passive Drain terminal of the P-channel MOSFET, one of four drain pins tied to the drain of the device; absolute maximum drain-source voltage is -40 V.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS -40 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID -7.2 A TC = 25 °C 1
Continuous drain current ID -5.7 A TC = 70 °C 1
Continuous drain current ID -5.5 A TA = 25 °C (a, b) 1
Continuous drain current ID -4.4 A TA = 70 °C (a, b) 1
Pulsed drain current IDM -20 A 1
Continuous source-drain diode current IS -3.5 A TC = 25 °C 1
Continuous source-drain diode current IS -2.1 A TA = 25 °C (a, b) 1
Avalanche current IAS -10 A L = 0.1 mH 1
Single-pulse avalanche energy EAS 5 mJ 1
Maximum power dissipation PD 4.2 W TC = 25 °C 1
Maximum power dissipation PD 2.7 W TC = 70 °C 1
Maximum power dissipation PD 2.5 W TA = 25 °C (a, b) 1
Maximum power dissipation PD 1.6 W TA = 70 °C (a, b) 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Maximum junction-to-ambient RthJA 40 50 °C/W t ≤ 10 s (a, c) 1
Maximum junction-to-foot RthJF 24 30 °C/W Steady state 1
Drain-source breakdown voltage VDS -40 V VGS = 0 V, ID = -250 μA 2
Gate-source threshold voltage VGS(th) -1.2 -2.5 V VDS = VGS, ID = -250 μA 2
Gate-source leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero gate voltage drain current IDSS -1 μA VDS = -40 V, VGS = 0 V 2
Zero gate voltage drain current IDSS -5 μA VDS = -40 V, VGS = 0 V, TJ = 55 °C 2
On-state drain current ID(on) -10 A VGS = -10 V 2
Drain-source on-state resistance RDS(on) 0.036 0.045 Ω VGS = -10 V, ID = -5 A 2
Drain-source on-state resistance RDS(on) 0.05 0.062 Ω VGS = -4.5 V, ID = -4 A 2
Gate resistance Rg 1 5.5 11 Ω f = 1 MHz 2
Total gate charge Qg 25 38 nC VDS = -20 V, VGS = -10 V, ID = -5 A 2
Total gate charge Qg 11.8 18 nC VDS = -20 V, VGS = -4.5 V, ID = -5 A 2
Turn-on delay time td(on) 7 14 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Rise time tr 12 24 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-off delay time td(off) 30 60 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Fall time tf 9 18 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-on delay time td(on) 44 80 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -4.5 V, Rg = 1 Ω 2
Rise time tr 33 60 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -4.5 V, Rg = 1 Ω 2
Turn-off delay time td(off) 28 55 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -4.5 V, Rg = 1 Ω 2
Fall time tf 13 25 ns VDD = -20 V, RL = 4 Ω, ID ≈ -5 A, VGEN = -4.5 V, Rg = 1 Ω 2
Pulse diode forward current ISM -20 A 2
Body diode voltage VSD -0.76 -1.2 V IS = -2 A, VGS = 0 V 2
Body diode reverse recovery time trr 27 50 ns IF = -2 A, di/dt = 100 A/μs, TJ = 25 °C 2
Body diode reverse recovery charge Qrr 19 35 nC IF = -2 A, di/dt = 100 A/μs, TJ = 25 °C 2

CAD (KiCad official)

  • Symbol: SI4447ADY-T1-GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si4447ady-t1-ge3-etched.step / si4447ady-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4447ady-t1-ge3.step / si4447ady-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 d3d234d23787f88c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF