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README

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SI4431BDY-T1-E3

Vishay Intertech · MOSFETs · SO-8

SI4431BDY-T1-E3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the P-channel MOSFET; continuous source (diode) current is rated -2.1 A (10 s) / -1.2 A (steady state).
2 S passive Source of the P-channel MOSFET, connected to the same source terminal as pins 1 and 3.
3 S passive Source of the P-channel MOSFET, connected to the same source terminal as pins 1 and 2.
4 G input Gate of the P-channel MOSFET; maximum gate-source voltage is ±20 V with threshold of -1.0 to -3.0 V.
5 D passive Drain of the P-channel MOSFET; drain-source voltage rated -30 V and pulsed drain current -30 A.
6 D passive Drain of the P-channel MOSFET, connected to the same drain terminal as pins 5, 7 and 8.
7 D passive Drain of the P-channel MOSFET, connected to the same drain terminal as pins 5, 6 and 8.
8 D passive Drain of the P-channel MOSFET, connected to the same drain terminal as pins 5, 6 and 7.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Triode/MOS Tube/Transistor
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate Threshold Voltage VGS(th) -3 -1 V VDS = VGS, ID = - 250 µA 2
Gate-Body Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current IDSS -1 µA VDS = - 30 V, VGS = 0 V 2
Zero Gate Voltage Drain Current (70 °C) IDSS -10 µA VDS = - 30 V, VGS = 0 V, TJ = 70 °C 2
On-State Drain Current ID(on) -30 A VDS = - 5 V, VGS = - 10 V 2
On-State Drain Current ID(on) -7 A VDS = - 5 V, VGS = - 4.5 V 2
Drain-Source On-State Resistance RDS(on) 0.023 0.03 Ω VGS = - 10 V, ID = - 7.5 A 2
Drain-Source On-State Resistance RDS(on) 0.036 0.05 Ω VGS = - 4.5 V, ID = - 5.8 A 2
Diode Forward Voltage VSD -0.78 -1.1 V IS = - 2.1 A, VGS = 0 V 2
Total Gate Charge Qg 13 20 nC VDS = - 15 V, VGS = - 5 V, ID = - 7.5 A 2
Turn-On Delay Time td(on) 10 20 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, RG = 6 Ω 2
Rise Time tr 10 20 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, RG = 6 Ω 2
Turn-Off Delay Time td(off) 70 110 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, RG = 6 Ω 2
Fall Time tf 47 70 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, RG = 6 Ω 2
Source-Drain Reverse Recovery Time trr 45 80 ns IF = - 2.1 A, dI/dt = 100 A/µs 2
Drain-Source Voltage VDS -30 V TA = 25 °C 1
Gate-Source Voltage VGS -20 20 V TA = 25 °C 1
Continuous Drain Current, 10 s ID -7.5 A TJ = 150 °C, TA = 25 °C, 10 s 1
Continuous Drain Current, Steady State ID -5.7 A TJ = 150 °C, TA = 25 °C, steady state 1
Continuous Drain Current, 10 s ID -6 A TJ = 150 °C, TA = 70 °C, 10 s 1
Continuous Drain Current, Steady State ID -4.6 A TJ = 150 °C, TA = 70 °C, steady state 1
Pulsed Drain Current IDM -30 A TA = 25 °C 1
Continuous Source Current, 10 s IS -2.1 A Diode conduction, 10 s 1
Continuous Source Current, Steady State IS -1.2 A Diode conduction, steady state 1
Maximum Power Dissipation, 10 s PD 2.5 W TA = 25 °C, 10 s 1
Maximum Power Dissipation, Steady State PD 1.5 W TA = 25 °C, steady state 1
Maximum Power Dissipation, 10 s PD 1.6 W TA = 70 °C, 10 s 1
Maximum Power Dissipation, Steady State PD 0.9 W TA = 70 °C, steady state 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Junction-to-Ambient Thermal Resistance, t ≤ 10 s RthJA 38 50 °C/W t ≤ 10 s 1
Junction-to-Ambient Thermal Resistance, Steady State RthJA 70 85 °C/W Steady State 1
Junction-to-Foot Thermal Resistance RthJF 22 28 °C/W Steady State 1
Forward Transconductance gfs 18 S VDS = - 15 V, ID = - 7.5 A 2

CAD (KiCad official)

  • Symbol: SI4431BDY-T1-E3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si4431bdy-t1-e3-etched.step / si4431bdy-t1-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4431bdy-t1-e3.step / si4431bdy-t1-e3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (8 pp, sha256 700a74765f1f305b, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF