SI4431-B1-FM from SILICON LABS, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD_RF	power_in	Supply input to all analog +1.7 V regulators, with a supply range of +1.8 to +3.6 V and a recommended +3.3 V.
2	TX	output	Transmit output is an open-drain PA output, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin.
3	RXp	input	Differential RF input pin of the LNA, connected through the application matching network.
4	RXn	input	Differential RF input pin of the LNA, connected through the application matching network.
5	NC	unconnected	No Connect pin, not connected internally to any circuitry.
6	ANT	output	Extra antenna or TR switch control output, a hardwired version of GPIO setting 11000 (Antenna 2) that can be controlled by the antdiv[2:0] bits in register 08h.
7	GPIO_0	bidirectional	General purpose digital I/O configurable through registers for functions such as MCU clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
8	GPIO_1	bidirectional	General purpose digital I/O configurable through registers for functions such as MCU clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
9	GPIO_2	bidirectional	General purpose digital I/O configurable through registers for functions such as MCU clock output, FIFO status, POR, wake-up timer, low battery detect, TRSW and antenna diversity control.
10	VR_DIG	power_out	Regulated output of the digital 1.7 V regulator, which requires a 1 µF decoupling capacitor.
11	NC	unconnected	Internally tied to the package paddle, so it should be left unconnected or connected to GND only.
12	VDD_DIG	power_in	Supply input to the digital +1.7 V regulator, with a supply range of +1.8 to +3.6 V and a recommended +3.3 V.
13	SDO	output	Serial readback digital output of the internal control registers, swinging 0 to VDD V.
14	SDI	input	Serial data input of the 4-line serial bus, a 0 to VDD V digital input.
15	SCLK	input	Serial clock input of the 4-line serial bus, a 0 to VDD V digital input; data is clocked in on positive edge transitions.
16	nSEL	input	Serial interface select (enable) input, a 0 to VDD V digital input that also signals burst read/write mode.
17	nIRQ	output	Microcontroller interrupt status output that is driven low when an interrupt event occurs, and needs no external pull-up unless multiple interrupt lines are tied together.
18	XOUT	output	Crystal oscillator output for an external 30 MHz crystal or source; an external source without crystal needs dc coupling at a nominal 0.8 VDC with at least 700 mVpp amplitude.
19	XIN	input	Crystal oscillator input for an external 30 MHz crystal, or left floating when driving an external source on XOUT.
20	SDN	input	Shutdown input, a 0 to VDD V digital input that must be 0 in all modes except shutdown; setting it to 1 fully shuts down the chip and loses register contents.
21	PADDLE_GND	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	SILICON LABS
Package	QFN-20(4x4)
Category	Radio Frequency Chip/Antenna
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage Range	VDD	1.8	3	3.6	V		7
Shutdown current	IShutdown		15	50	nA	RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF	7
Standby current	IStandby		450	800	nA	Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF	7
Sleep current	ISleep		1		µA	RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF	7
Ready mode current	IReady		800		µA	Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled	7
Tune mode current	ITune		8.5		mA	Synthesizer and regulators enabled	7
RX mode current	IRX		18.5		mA		7
TX mode current +13 dBm	ITX_+13		30		mA	txpow[2:0] = 110 (+13 dBm)	7
TX mode current +1 dBm	ITX_+1		17		mA	txpow[2:0] = 010 (+1 dBm)	7
Synthesizer Frequency Range	FSYN	240		930	MHz	Si4431/32	8
Reference Frequency Input Level	fREF_LV	0.7		1.6	V	External reference signal driving XOUT pin, peak-to-peak (VPP)	8
Residual FM	FRMS		2	4	kHzRMS	Integrated over 250 kHz bandwidth (500 Hz lower bound of integration)	8
RX Frequency Range	FRX	240		930	MHz	Si4431/32	9
RX Channel Bandwidth	BW	2.6		620	kHz		9
BER Variation vs Power Level	PRX_RES		0	0.1	ppm	Up to +5 dBm Input Level	9
Spurious Emissions RX	POB_RX1			-54	dBm	Measured at RX pins	9
TX Frequency Range	FTX	240		930	MHz	Si4431/32	10
FSK Data Rate	DRFSK	0.123		256	kbps		10
OOK Data Rate	DROOK	0.123		40	kbps		10
Modulation Deviation 860-960 MHz	∆f1	0.625		320	kHz	860-960 MHz	10
Modulation Deviation 240-860 MHz	∆f2	0.625		160	kHz	240-860 MHz	10
Output Power Range	PTX	-8		13	dBm	Si4430/31	10
Spurious Emissions TX <1 GHz	POB-TX1			-54	dBm	POUT = +13 dBm, Frequencies <1 GHz	10
Spurious Emissions TX 1-12.75 GHz	POB-TX2			-54	dBm	1-12.75 GHz, excluding harmonics	10
2nd Harmonic	P2HARM			-42	dBm	Using reference design TX matching network and filter with max output power	10
3rd Harmonic	P3HARM			-42	dBm	Using reference design TX matching network and filter with max output power	10
Digital IO Rise Time	TRISE			8	ns	0.1 x VDD to 0.9 x VDD, CL= 5 pF	12
Digital IO Fall Time	TFALL			8	ns	0.9 x VDD to 0.1 x VDD, CL= 5 pF	12
Digital IO Input Capacitance	CIN			1	pF		12
Digital IO Logic High Input Voltage	VIH	-0.6			V	VDD, 0.6 (min, relative to VDD)	12
Digital IO Logic Low Input Voltage	VIL			0.6	V		12
Digital IO Input Current	IIN	-100		100	nA	0<VIN< VDD	12
Digital IO Logic Low Output Voltage	VOL			0.6	V	IOL<1 mA sink, VDD=1.8 V	12
GPIO Rise Time	TRISE			8	ns	0.1 x VDD to 0.9 x VDD, CL= 10 pF, DRV<1:0>=HH	12
GPIO Fall Time	TFALL			8	ns	0.9 x VDD to 0.1 x VDD, CL= 10 pF, DRV<1:0>=HH	12
GPIO Input Capacitance	CIN			1	pF		12
GPIO Logic Low Input Voltage	VIL			0.6	V		12
GPIO Input Current	IIN	-100		100	nA	0<VIN< VDD	12
GPIO Input Current If Pullup is Activated	IINP	5		25	µA	VIL=0 V	12
GPIO Maximum Output Current LL	IOmaxLL	0.1	0.5	0.8	mA	DRV<1:0>=LL	12
GPIO Maximum Output Current LH	IOmaxLH	0.9	2.3	3.5	mA	DRV<1:0>=LH	12
GPIO Maximum Output Current HL	IOmaxHL	1.5	3.1	4.8	mA	DRV<1:0>=HL	12
GPIO Maximum Output Current HH	IOmaxHH	1.8	3.6	5.4	mA	DRV<1:0>=HH	12
GPIO Logic Low Output Voltage	VOL			0.6	V	IOL< IOmax sink, VDD=1.8 V	12
VDD to GND	VDD	-0.3		3.6	V		13
Instantaneous VRF-peak to GND on TX Output Pin	VRF-peak	-0.3		8	V		13
Sustained VRF-peak to GND on TX Output Pin	VRF-peak	-0.3		6.5	V		13
Voltage on Digital Control Inputs		-0.3		0.3	V	Max is VDD + 0.3 V	13
Voltage on Analog Inputs		-0.3		0.3	V	Max is VDD + 0.3 V	13
RX Input Power				10	dBm		13
Operating Ambient Temperature Range	TA	-40		85	°C		13
Thermal Impedance	θJA		30		°C/W		13
Junction Temperature	TJ			125	°C		13
Storage Temperature Range	TSTG	-55		125	°C		13

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		wireless knowledge base at www.silabs.com/support/knowledgebase.	63

CAD (KiCad official)

Symbol: SI4431-B1-FM
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: QFN-20(4x4) (KiCad packages3D, STEP)
3D model files: si4431-b1-fm-etched.step / si4431-b1-fm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4431-b1-fm.step / si4431-b1-fm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SILICON LABS datasheet (74 pp, sha256 a0dc9f652a3ee30e, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SI4431-B1-FM

Verified SI4431-B1-FM

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README