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SI4420BDY-T1-E3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SI4420BDY-T1-E3
Vishay Intertech · MOSFETs · SOIC-8
SI4420BDY-T1-E3 from Vishay Intertech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied to pins 2 and 3. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to pins 1 and 3. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to pins 1 and 2. |
| 4 | G | input | Gate terminal; VGS rated ±20 V, threshold 1.0 to 3.0 V at ID = 250 µA. |
| 5 | D | passive | Drain terminal, tied to pins 6, 7 and 8; VDS rated 30 V. |
| 6 | D | passive | Drain terminal, tied to pins 5, 7 and 8; VDS rated 30 V. |
| 7 | D | passive | Drain terminal, tied to pins 5, 6 and 8; VDS rated 30 V. |
| 8 | D | passive | Drain terminal, tied to pins 5, 6 and 7; VDS rated 30 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOIC-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 30 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 13.5 | A | TA = 25 °C, t ≤ 10 s | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 9.5 | A | TA = 25 °C, steady state | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 10.8 | A | TA = 70 °C, t ≤ 10 s | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 7.5 | A | TA = 70 °C, steady state | 1 | ||
| Pulsed Drain Current | IDM | 50 | A | 1 | |||
| Continuous Source Current (Diode Conduction) | IS | 2.3 | A | t ≤ 10 s | 1 | ||
| Continuous Source Current (Diode Conduction) | IS | 1.26 | A | steady state | 1 | ||
| Single Pulse Avalanche Current | IAS | 20 | A | L = 0.1 mH | 1 | ||
| Avalanche Energy | EAS | 20 | mJ | 1 | |||
| Maximum Power Dissipation | PD | 2.5 | W | TA = 25 °C, t ≤ 10 s | 1 | ||
| Maximum Power Dissipation | PD | 1.4 | W | TA = 25 °C, steady state | 1 | ||
| Maximum Power Dissipation | PD | 1.6 | W | TA = 70 °C, t ≤ 10 s | 1 | ||
| Maximum Power Dissipation | PD | 0.9 | W | TA = 70 °C, steady state | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Maximum Junction-to-Ambient | RthJA | 40 | 50 | °C/W | t < 10 s | 1 | |
| Maximum Junction-to-Ambient | RthJA | 70 | 90 | °C/W | steady state | 1 | |
| Maximum Junction-to-Foot (Drain) | RthJF | 23 | 28 | °C/W | steady state | 1 | |
| Gate Threshold Voltage | VGS(th) | 1 | 3 | V | VDS = VGS, ID = 250 µA | 2 | |
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 30 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 5 | µA | VDS = 30 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current | ID(on) | 30 | A | VDS ≥ 5 V, VGS = 10 V | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.007 | 0.0085 | Ω | VGS = 10 V, ID = 13.5 A | 2 | |
| Drain-Source On-State Resistance | RDS(on) | 0.009 | 0.011 | Ω | VGS = 4.5 V, ID = 11 A | 2 | |
| Diode Forward Voltage | VSD | 0.75 | 1.1 | V | IS = 2.3 A, VGS = 0 V | 2 | |
| Gate Charge | Qg | 16 | 25 | nC | VDS = 15 V, VGS = 5 V, ID = 13.5 A | 2 | |
| Total Gate Charge | Qgt | 31 | 50 | nC | VDS = 15 V, VGS = 10 V, ID = 13.5 A | 2 | |
| Gate Resistance | Rg | 0.5 | 1 | 1.5 | Ω | 2 | |
| Turn-On Delay Time | td(on) | 15 | 25 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Rise Time | tr | 11 | 18 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 40 | 60 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Fall Time | tf | 12 | 20 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Source-Drain Reverse Recovery Time | trr | 30 | 50 | ns | IF = 2.3 A, dI/dt = 100 A/µs | 2 |
CAD (KiCad official)
- Symbol:
SI4420BDY-T1-E3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
si4420bdy-t1-e3-etched.step/si4420bdy-t1-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si4420bdy-t1-e3.step/si4420bdy-t1-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (8 pp, sha256
02a90e28bf213164, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SI4420BDY-T1-E3
**Vishay Intertech** · MOSFETs · SOIC-8
SI4420BDY-T1-E3 from Vishay Intertech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied to pins 2 and 3. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to pins 1 and 3. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to pins 1 and 2. |
| 4 | G | input | Gate terminal; VGS rated ±20 V, threshold 1.0 to 3.0 V at ID = 250 µA. |
| 5 | D | passive | Drain terminal, tied to pins 6, 7 and 8; VDS rated 30 V. |
| 6 | D | passive | Drain terminal, tied to pins 5, 7 and 8; VDS rated 30 V. |
| 7 | D | passive | Drain terminal, tied to pins 5, 6 and 8; VDS rated 30 V. |
| 8 | D | passive | Drain terminal, tied to pins 5, 6 and 7; VDS rated 30 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOIC-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | | | 30 | V | | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Continuous Drain Current (TJ = 150 °C) | ID | | | 13.5 | A | TA = 25 °C, t ≤ 10 s | 1 |
| Continuous Drain Current (TJ = 150 °C) | ID | | | 9.5 | A | TA = 25 °C, steady state | 1 |
| Continuous Drain Current (TJ = 150 °C) | ID | | | 10.8 | A | TA = 70 °C, t ≤ 10 s | 1 |
| Continuous Drain Current (TJ = 150 °C) | ID | | | 7.5 | A | TA = 70 °C, steady state | 1 |
| Pulsed Drain Current | IDM | | | 50 | A | | 1 |
| Continuous Source Current (Diode Conduction) | IS | | | 2.3 | A | t ≤ 10 s | 1 |
| Continuous Source Current (Diode Conduction) | IS | | | 1.26 | A | steady state | 1 |
| Single Pulse Avalanche Current | IAS | | | 20 | A | L = 0.1 mH | 1 |
| Avalanche Energy | EAS | | | 20 | mJ | | 1 |
| Maximum Power Dissipation | PD | | | 2.5 | W | TA = 25 °C, t ≤ 10 s | 1 |
| Maximum Power Dissipation | PD | | | 1.4 | W | TA = 25 °C, steady state | 1 |
| Maximum Power Dissipation | PD | | | 1.6 | W | TA = 70 °C, t ≤ 10 s | 1 |
| Maximum Power Dissipation | PD | | | 0.9 | W | TA = 70 °C, steady state | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Maximum Junction-to-Ambient | RthJA | | 40 | 50 | °C/W | t < 10 s | 1 |
| Maximum Junction-to-Ambient | RthJA | | 70 | 90 | °C/W | steady state | 1 |
| Maximum Junction-to-Foot (Drain) | RthJF | | 23 | 28 | °C/W | steady state | 1 |
| Gate Threshold Voltage | VGS(th) | 1 | | 3 | V | VDS = VGS, ID = 250 µA | 2 |
| Gate-Body Leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | µA | VDS = 30 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 5 | µA | VDS = 30 V, VGS = 0 V, TJ = 55 °C | 2 |
| On-State Drain Current | ID(on) | 30 | | | A | VDS ≥ 5 V, VGS = 10 V | 2 |
| Drain-Source On-State Resistance | RDS(on) | | 0.007 | 0.0085 | Ω | VGS = 10 V, ID = 13.5 A | 2 |
| Drain-Source On-State Resistance | RDS(on) | | 0.009 | 0.011 | Ω | VGS = 4.5 V, ID = 11 A | 2 |
| Diode Forward Voltage | VSD | | 0.75 | 1.1 | V | IS = 2.3 A, VGS = 0 V | 2 |
| Gate Charge | Qg | | 16 | 25 | nC | VDS = 15 V, VGS = 5 V, ID = 13.5 A | 2 |
| Total Gate Charge | Qgt | | 31 | 50 | nC | VDS = 15 V, VGS = 10 V, ID = 13.5 A | 2 |
| Gate Resistance | Rg | 0.5 | 1 | 1.5 | Ω | | 2 |
| Turn-On Delay Time | td(on) | | 15 | 25 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 |
| Rise Time | tr | | 11 | 18 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 |
| Turn-Off Delay Time | td(off) | | 40 | 60 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 |
| Fall Time | tf | | 12 | 20 | ns | VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 |
| Source-Drain Reverse Recovery Time | trr | | 30 | 50 | ns | IF = 2.3 A, dI/dt = 100 A/µs | 2 |
## CAD (KiCad official)
- Symbol: `SI4420BDY-T1-E3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `si4420bdy-t1-e3-etched.step` / `si4420bdy-t1-e3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si4420bdy-t1-e3.step` / `si4420bdy-t1-e3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602992237114908672) (8 pp, sha256 `02a90e28bf213164`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/si4420bdy-t1-e3-datasheet.pdf)