SI4228DY-T1-GE3

{
  "schema_version": 1,
  "type": "component",
  "slug": "si4228dy-t1-ge3",
  "title": "SI4228DY-T1-GE3",
  "brief": "Vishay Intertech MOSFETs, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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  "component": {
    "mpn": "SI4228DY-T1-GE3",
    "manufacturer": "Vishay Intertech",
    "package": "SO-8",
    "pin_count": 8,
    "category": "Transistors/Thyristors",
    "subcategory": "MOSFETs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923335900073985",
    "parts": {
      "symbol": "si4228dy-t1-ge3.kicad_sym",
      "footprint": "si4228dy-t1-ge3.kicad_mod",
      "model_3d": "si4228dy-t1-ge3-etched.glb",
      "model_3d_plain": "si4228dy-t1-ge3.glb",
      "model_3d_step": "si4228dy-t1-ge3-etched.step",
      "model_3d_step_plain": "si4228dy-t1-ge3.step",
      "lbr": "si4228dy-t1-ge3.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "S1",
        "type": "passive",
        "description": "Source of MOSFET 1. Bonded together with pin 1 as the low-current source terminal of the first N-channel FET."
      },
      {
        "number": "2",
        "name": "G1",
        "type": "input",
        "description": "Gate of MOSFET 1. VGS rated ±12 V, VGS(th) 0.6 V to 1.4 V; drive to ≥4.5 V for full enhancement."
      },
      {
        "number": "3",
        "name": "S2",
        "type": "passive",
        "description": "Source of MOSFET 2. Source terminal of the second independent N-channel FET."
      },
      {
        "number": "4",
        "name": "G2",
        "type": "input",
        "description": "Gate of MOSFET 2. VGS rated ±12 V; drive to ≥4.5 V for full enhancement."
      },
      {
        "number": "5",
        "name": "D2",
        "type": "passive",
        "description": "Drain of MOSFET 2. Paralleled internally with pin 6 for current-carrying capability; VDS 25 V max."
      },
      {
        "number": "6",
        "name": "D2",
        "type": "passive",
        "description": "Drain of MOSFET 2 (paralleled with pin 5). Both drain pins of FET2 should be tied together on the PCB for full current rating and heat sinking."
      },
      {
        "number": "7",
        "name": "D1",
        "type": "passive",
        "description": "Drain of MOSFET 1 (paralleled with pin 8). VDS 25 V max."
      },
      {
        "number": "8",
        "name": "D1",
        "type": "passive",
        "description": "Drain of MOSFET 1 (paralleled with pin 7). Both drain pins of FET1 should be tied together on the PCB for full current rating and heat sinking."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923335900073985",
        "pages": 9,
        "sha256": "38d59c0301776d7d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "si4228dy-t1-ge3-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "73abd6b807696e322a19fbf9bc362b8e70a6a5a91f253e33cb68bdb5d0f73fdd",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Vishay Intertech",
      "Package": "SO-8",
      "Category": "Transistors/Thyristors",
      "Pins": "8"
    }
  },
  "variants": [
    {
      "mpn": "SI4228DY-T1-GE3",
      "kind": "packaging"
    }
  ],
  "sections": [
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    "readme",
    "breadcrumbs",
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  "discovery_triggers": [
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  "discovery_pitch": "SI4228DY-T1-GE3 (Vishay Intertech) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
  },
  "files": [
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    "si4228dy-t1-ge3.lbr",
    "docs/hero.png",
    "docs/si4228dy-t1-ge3-datasheet.pdf",
    "viewers/symbol.html",
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  "visibility": {
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  },
  "updated_at": "2026-09-25T05:57:47.893Z"
}