component

SI4143DY-T1-GE3

Public Made by Adom

by adom

Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorssi4143dy-t1-ge3factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers si4143dy-t1-ge3: viewers · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3-etched.glb Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3-etched.step si4143dy-t1-ge3: factory component page (tier=lcsc) · Ray 17d ago
si4143dy-t1-ge3-hero.glb si4143dy-t1-ge3: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
si4143dy-t1-ge3-hero.overlay.json Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3.glb Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3.kicad_mod Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3.kicad_sym Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3.lbr Publish 0.1.0 · Ray 17d ago
si4143dy-t1-ge3.step Publish 0.1.0 · Ray 17d ago

SI4143DY-T1-GE3

Vishay Intertech · MOSFETs · SO-8

SI4143DY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the P-channel MOSFET; device VDS is rated -30 V and continuous source-drain diode current IS is -5 A at TC = 25 °C.
2 S passive Source terminal of the P-channel MOSFET; device VDS is rated -30 V and continuous source-drain diode current IS is -5 A at TC = 25 °C.
3 S passive Source terminal of the P-channel MOSFET; device VDS is rated -30 V and continuous source-drain diode current IS is -5 A at TC = 25 °C.
4 G input Gate terminal of the P-channel MOSFET; gate-source voltage is limited to ±25 V.
5 D passive Drain terminal of the P-channel MOSFET; continuous drain current is -25.3 A at TC = 25 °C, with pulsed drain current IDM of -70 A.
6 D passive Drain terminal of the P-channel MOSFET; continuous drain current is -25.3 A at TC = 25 °C, with pulsed drain current IDM of -70 A.
7 D passive Drain terminal of the P-channel MOSFET; continuous drain current is -25.3 A at TC = 25 °C, with pulsed drain current IDM of -70 A.
8 D passive Drain terminal of the P-channel MOSFET; continuous drain current is -25.3 A at TC = 25 °C, with pulsed drain current IDM of -70 A.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -30 V 1
Gate-Source Voltage VGS -25 25 V 1
Continuous Drain Current ID -25.3 A TJ = 150 °C, TC = 25 °C 1
Continuous Drain Current ID -20.2 A TJ = 150 °C, TC = 70 °C 1
Continuous Drain Current ID -17.7 A TJ = 150 °C, TA = 25 °C (notes a, b) 1
Continuous Drain Current ID -14.1 A TJ = 150 °C, TA = 70 °C (notes a, b) 1
Pulsed Drain Current IDM -70 A t = 300 μs 1
Continuous Source-Drain Diode Current IS -5 A TC = 25 °C 1
Continuous Source-Drain Diode Current IS -2.4 A TA = 25 °C (notes a, b) 1
Avalanche Current IAS -30 A L = 0.1 mH 1
Single Pulse Avalanche Energy EAS 45 mJ 1
Maximum Power Dissipation PD 6 W TC = 25 °C 1
Maximum Power Dissipation PD 3.8 W TC = 70 °C 1
Maximum Power Dissipation PD 2.9 W TA = 25 °C (notes a, b) 1
Maximum Power Dissipation PD 1.9 W TA = 70 °C (notes a, b) 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Maximum Junction-to-Ambient RthJA 36 43 °C/W t ≤ 10 s (notes a, c) 1
Maximum Junction-to-Foot RthJF 16 21 °C/W Steady state 1
Maximum Junction-to-Ambient (steady state) RthJA 84 °C/W Steady state (note c) 1
Drain-Source Breakdown Voltage VDS -30 V VGS = 0 V, ID = -250 μA 2
Gate-Source Threshold Voltage VGS(th) -1 -2.5 V VDS = VGS, ID = -250 μA 2
Gate-Source Leakage IGSS -100 100 nA VDS = 0 V, VGS = ±25 V 2
Zero Gate Voltage Drain Current IDSS -1 μA VDS = -30 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS -5 μA VDS = -30 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) -30 A VDS ≥ -10 V, VGS = -10 V 2
Drain-Source On-State Resistance RDS(on) 0.0051 0.0062 Ω VGS = -10 V, ID = -12 A 2
Drain-Source On-State Resistance RDS(on) 0.0061 0.0074 Ω VGS = -6 V, ID = -8 A 2
Drain-Source On-State Resistance RDS(on) 0.0076 0.0092 Ω VGS = -4.5 V, ID = -5 A 2
Total Gate Charge Qg 111 167 nC VDS = -15 V, VGS = -10 V, ID = -18 A 2
Total Gate Charge Qg 54 81 nC VDS = -15 V, VGS = -4.5 V, ID = -18 A 2
Gate Resistance Rg 0.5 2.3 4.6 Ω f = 1 MHz 2
Turn-On Delay Time td(on) 18 27 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω 2
Rise Time tr 8 16 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 71 107 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω 2
Fall Time tf 15 23 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-On Delay Time td(on) 59 89 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω 2
Rise Time tr 60 90 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 56 84 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω 2
Fall Time tf 29 44 ns VDD = -15 V, RL = 1.5 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω 2
Continuous Source-Drain Diode Current IS -5 A TC = 25 °C 2
Pulse Diode Forward Current ISM -70 A 2
Body Diode Voltage VSD -0.78 -1.2 V IS = -10 A, VGS = 0 V 2
Body Diode Reverse Recovery Time trr 42 63 ns IF = -10 A, dI/dt = 100 A/μs, TJ = 25 °C 2
Body Diode Reverse Recovery Charge Qrr 37 56 nC IF = -10 A, dI/dt = 100 A/μs, TJ = 25 °C 2

CAD (KiCad official)

  • Symbol: SI4143DY-T1-GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si4143dy-t1-ge3-etched.step / si4143dy-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4143dy-t1-ge3.step / si4143dy-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 5d8d2200fe9151e7, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF