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SI3429EDV-T1-GE3

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Vishay Intertech MOSFETs, TSOP-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI3429EDV-T1-GE3

Vishay Intertech · MOSFETs · TSOP-6

SI3429EDV-T1-GE3 from Vishay Intertech, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D passive Drain, connected internally with pins 2, 5 and 6; VDS rated -20 V and the drain pins also provide the thermal path from the package.
2 D passive Drain, connected internally with pins 1, 5 and 6; VDS rated -20 V and continuous drain current up to -8 A (package limited).
3 G input Gate with built-in ESD protection (typical 3000 V); gate-source voltage limit is ±8 V.
4 S passive Source of the P-channel MOSFET; continuous source-drain diode current is -3.5 A at TC = 25 °C.
5 D passive Drain, connected internally with pins 1, 2 and 6; pulsed drain current is -40 A (t = 300 μs).
6 D passive Drain, connected internally with pins 1, 2 and 5; should be tied to a copper spreading plane for heat removal.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package TSOP-6
Category Triode/MOS Tube/Transistor
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -20 V 1
Gate-Source Voltage VGS -8 8 V 1
Continuous Drain Current ID -8 A TC = 25 °C 1
Continuous Drain Current ID -6.4 A TA = 70 °C (notes b, c) 1
Pulsed Drain Current IDM -40 A t = 300 μs 1
Continuous Source-Drain Diode Current IS -3.5 A TC = 25 °C 1
Continuous Source-Drain Diode Current IS -1.7 A TA = 25 °C (notes b, c) 1
Maximum Power Dissipation PD 4.2 W TC = 25 °C 1
Maximum Power Dissipation PD 2.7 W TC = 70 °C 1
Maximum Power Dissipation PD 2 W TA = 25 °C (notes b, c) 1
Maximum Power Dissipation PD 1.3 W TA = 70 °C (notes b, c) 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Maximum Junction-to-Ambient RthJA 45 62.5 °C/W t ≤ 5 s (notes b, d) 1
Maximum Junction-to-Foot (Drain) RthJF 25 30 °C/W Steady State 1
Drain-Source Breakdown Voltage VDS -20 V VGS = 0 V, ID = -250 μA 2
Gate-Source Threshold Voltage VGS(th) -0.4 -1 V VDS = VGS, ID = -250 μA 2
Gate-Source Leakage IGSS -10 10 μA VDS = 0 V, VGS = ± 8 V 2
Gate-Source Leakage IGSS -1 1 μA VDS = 0 V, VGS = ± 4.5 V 2
Zero Gate Voltage Drain Current IDSS -1 μA VDS = -20 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS -10 μA VDS = -20 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) -15 A VDS ≤ -5 V, VGS = -4.5 V 2
Drain-Source On-State Resistance RDS(on) 0.0175 0.021 Ω VGS = -4.5 V, ID = -4 A 2
Drain-Source On-State Resistance RDS(on) 0.02 0.024 Ω VGS = -2.5 V, ID = -4 A 2
Drain-Source On-State Resistance RDS(on) 0.025 0.038 Ω VGS = -1.8 V, ID = -2 A 2
Total Gate Charge Qg 78.2 118 nC VDS = -10 V, VGS = -8 V, ID = -8 A 2
Total Gate Charge Qg 43.2 65 nC VDS = -10 V, VGS = -4.5 V, ID = -8 A 2
Gate Resistance Rg 1.8 9.4 18.8 Ω f = 1 MHz 2
Turn-On Delay Time td(on) 35 53 ns VDD = -10 V, RL = 1.56 Ω, ID ≅ -6.4 A, VGEN = -4.5 V, Rg = 1 Ω 2
Rise Time tr 30 45 ns 2
Turn-Off Delay Time td(off) 174 261 ns 2
Fall Time tf 58 87 ns 2
Turn-On Delay Time td(on) 10 20 ns VDD = -10 V, RL = 1.56 Ω, ID ≅ -6.4 A, VGEN = -8 V, Rg = 1 Ω 2
Rise Time tr 17 26 ns 2
Turn-Off Delay Time td(off) 210 315 ns 2
Fall Time tf 64 96 ns 2
Continuous Source-Drain Diode Current IS -3.5 A TC = 25 °C 2
Pulse Diode Forward Current ISM -40 A 2
Body Diode Voltage VSD -0.8 -1.2 V IS = -6.4 A, VGS = 0 V 2
Body Diode Reverse Recovery Time trr 28 42 ns IF = -6.4 A, dI/dt = 100 A/μs, TJ = 25 °C 2
Body Diode Reverse Recovery Charge Qrr 16 24 nC 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper pins 1,2,5, and 6. The copper plane connects the drain pins 8

CAD (KiCad official)

  • Symbol: SI3429EDV-T1-GE3
  • Footprint: Package_SO:TSOP-6_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-6 (KiCad packages3D, STEP)
  • 3D model files: si3429edv-t1-ge3-etched.step / si3429edv-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si3429edv-t1-ge3.step / si3429edv-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (11 pp, sha256 32bda631fab2d152, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF