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SI2371EDS-T1-GE3

Public Made by Adom

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Vishay Intertech MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI2371EDS-T1-GE3

Vishay Intertech · MOSFETs · SOT-23

SI2371EDS-T1-GE3 from Vishay Intertech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the P-channel MOSFET; the datasheet gives gate-source voltage VGS as ±12 V absolute maximum.
2 S passive Source of the P-channel MOSFET; continuous source-drain diode current is limited to -1.4 A at TC = 25 °C.
3 D passive Drain of the P-channel MOSFET, which also serves as the thermal connection to the PC board; drain-source voltage is -30 V and continuous drain current is -4.8 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: SI2371EDS-T1-GE3
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: si2371eds-t1-ge3-etched.step / si2371eds-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si2371eds-t1-ge3.step / si2371eds-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (10 pp, sha256 5a563f15cfe8c0e7, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF