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Contents

README

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SI2303CDS-T1-E3

Vishay Intertech · MOSFETs · SOT-23

SI2303CDS-T1-E3 from Vishay Intertech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the P-channel MOSFET; gate-source voltage is limited to ±20 V (VGS).
2 S passive Source of the MOSFET; continuous source-drain diode current is limited to -1.75 A at TC = 25 °C (-0.83 A at TA = 25 °C).
3 D passive Drain of the MOSFET; drain-source voltage is -30 V (VDS) with continuous drain current of -2.7 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: SI2303CDS-T1-E3
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: si2303cds-t1-e3-etched.step / si2303cds-t1-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si2303cds-t1-e3.step / si2303cds-t1-e3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 6d888d9830c64ac1, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF