component

SI2151-A10-GMR

Public Made by Adom

by adom

SILICON LABS Video Interface ICs, QFN-24(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232si2151-a10-gmrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SI2151-A10-GMR

SILICON LABS · Video Interface ICs · QFN-24(3x3)

SI2151-A10-GMR from SILICON LABS, in a QFN-24(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO2 bidirectional General-purpose I/O pin of the control interface.
2 SDA bidirectional Serial data line of the control interface to the AV SoC.
3 SCL input Serial clock line of the control interface from the AV SoC.
4 AGC2 output AGC output to the demodulator, shown in the block diagram.
5 AGC1 output AGC output to the demodulator, shown in the block diagram.
6 GND power_in Ground connection.
7 VDDL power_in 1.8 V supply input (VDDL = 1.8 V in the electrical specifications); the integrated LDO allows 3.3 V single-supply operation.
8 GND power_in Ground connection.
9 VDDH power_in 3.3 V supply input (VDDH = 3.3 V in the electrical specifications).
10 LIF_N output Negative side of the differential LIF output, with programmable differential output voltage of 0.5 to 2.0 Vppd.
11 LIF_P output Positive side of the differential LIF output, with programmable differential output voltage of 0.5 to 2.0 Vppd.
12 XOUT output Crystal oscillator clock output buffer, shown in the block diagram.
13 XTAL_I input Crystal oscillator input.
14 XTAL_O output Crystal oscillator output.
15 VDDH power_in 3.3 V supply input (VDDH = 3.3 V in the electrical specifications).
16 GND power_in Ground connection.
17 VDDH power_in 3.3 V supply input (VDDH = 3.3 V in the electrical specifications).
18 NC unconnected No connect.
19 RF_REF passive RF reference pin of the antenna input, which covers 42 to 1002 MHz.
20 RF_IP input Positive RF antenna input, with an RF input frequency range of 42 to 1002 MHz.
21 GND power_in Ground connection.
22 RF_IN input Negative RF antenna input, with an RF input frequency range of 42 to 1002 MHz.
23 ADDR input Address select input of the control interface.
24 GPIO1 bidirectional General-purpose I/O pin of the control interface.
25 GND PAD power_in Exposed center ground pad of the QFN-24 package.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-24(3x3)
Category Communication Interface Chip/UART/485/232
Pins 25

CAD (KiCad official)

  • Symbol: SI2151-A10-GMR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm
  • 3D model: QFN-24(3x3) (KiCad packages3D, STEP)
  • 3D model files: si2151-a10-gmr-etched.step / si2151-a10-gmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si2151-a10-gmr.step / si2151-a10-gmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (2 pp, sha256 1bf1548e40caa131, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF