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SI1330EDL-T1-GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SC-70-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSI1330EDL-T1-GE3
Vishay Intertech · MOSFETs · SC-70-3
SI1330EDL-T1-GE3 from Vishay Intertech, in a SC-70-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal, with a gate-source voltage limit of ±20 V and the device rated ESD protected to 2000 V. |
| 2 | S | passive | Source terminal, with a continuous source (diode conduction) current rating IS of 0.26 A at TA = 25 °C for 5 s and 0.23 A in steady state. |
| 3 | D | passive | Drain terminal, with a drain-source voltage limit VDS of 60 V and a continuous drain current ID of 0.25 A at TA = 25 °C for 5 s and 0.24 A in steady state. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SC-70-3 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | VDS | 60 | V | VGS = 0 V, ID = 10 µA | 2 | ||
| Gate-Threshold Voltage | VGS(th) | 1 | 2 | 2.5 | V | VDS = VGS, ID = 250 µA | 2 |
| Gate-Body Leakage | IGSS | -1 | 1 | µA | VDS = 0 V, VGS = ± 10 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 60 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 10 | µA | VDS = 60 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current | ID(on) | 0.5 | A | VGS = 10 V, VDS = 7.5 V | 2 | ||
| On-State Drain Current | ID(on) | 0.4 | A | VGS = 4.5 V, VDS = 10 V | 2 | ||
| On-State Drain Current | ID(on) | 0.05 | A | VGS = 3 V, VDS = 10 V | 2 | ||
| Drain-Source On-Resistance | RDS(on) | 1 | 2.5 | Ω | VGS = 10 V, ID = 0.25 A | 2 | |
| Drain-Source On-Resistance | RDS(on) | 1.4 | 3 | Ω | VGS = 4.5 V, ID = 0.2 A | 2 | |
| Drain-Source On-Resistance | RDS(on) | 3 | 8 | Ω | VGS = 3 V, ID = 0.025 A | 2 | |
| Diode Forward Voltage | VSD | 0.83 | 1.2 | V | IS = 0.23 A, VGS = 0 V | 2 | |
| Total Gate Charge | Qg | 0.4 | 0.6 | nC | VDS = 10 V, VGS = 4.5 V, ID ≅ 0.25 A | 2 | |
| Turn-On Time (delay) | td(on) | 3.8 | 10 | ns | VDD = 30 V, RL = 150 Ω, ID ≅ 0.2 A, VGEN = 10 V, Rg = 10 Ω | 2 | |
| Turn-On Time (rise) | tr | 4.8 | 15 | ns | VDD = 30 V, RL = 150 Ω, ID ≅ 0.2 A, VGEN = 10 V, Rg = 10 Ω | 2 | |
| Turn-Off Time (delay) | td(off) | 12.8 | 20 | ns | VDD = 30 V, RL = 150 Ω, ID ≅ 0.2 A, VGEN = 10 V, Rg = 10 Ω | 2 | |
| Turn-Off Time (fall) | tf | 9.6 | 15 | ns | VDD = 30 V, RL = 150 Ω, ID ≅ 0.2 A, VGEN = 10 V, Rg = 10 Ω | 2 | |
| Drain-Source Voltage | VDS | 60 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 0.25 | A | TA = 25 °C, t ≤ 5 s | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 0.24 | A | TA = 25 °C, steady state | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 0.2 | A | TA = 70 °C, t ≤ 5 s | 1 | ||
| Continuous Drain Current (TJ = 150 °C) | ID | 0.19 | A | TA = 70 °C, steady state | 1 | ||
| Pulsed Drain Current | IDM | 1 | A | 1 | |||
| Continuous Source Current (Diode Conduction) | IS | 0.26 | A | t ≤ 5 s | 1 | ||
| Continuous Source Current (Diode Conduction) | IS | 0.23 | A | Steady State | 1 | ||
| Maximum Power Dissipation | PD | 0.31 | W | TA = 25 °C, t ≤ 5 s | 1 | ||
| Maximum Power Dissipation | PD | 0.28 | W | TA = 25 °C, steady state | 1 | ||
| Maximum Power Dissipation | PD | 0.2 | W | TA = 70 °C, t ≤ 5 s | 1 | ||
| Maximum Power Dissipation | PD | 0.18 | W | TA = 70 °C, steady state | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Maximum Junction-to-Ambient | RthJA | 355 | 400 | °C/W | t ≤ 5 s | 1 | |
| Maximum Junction-to-Ambient | RthJA | 380 | 450 | °C/W | Steady State | 1 | |
| Maximum Junction-to-Foot (Drain) | RthJF | 285 | 340 | °C/W | Steady State | 1 |
CAD (KiCad official)
- Symbol:
SI1330EDL-T1-GE3 - Footprint:
Package_TO_SOT_SMD:SOT-323_SC-70 - 3D model: SC-70-3 (KiCad packages3D, STEP)
- 3D model files:
si1330edl-t1-ge3-etched.step/si1330edl-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si1330edl-t1-ge3.step/si1330edl-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (5 pp, sha256
eefb39f6c26dce7c, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).