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SI1308EDL-T1-GE3

Public Made by Adom

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Vishay Intertech MOSFETs, SOT-323. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Ray si1308edl-t1-ge3: specified limits as data (metadata.characteristics, 41 rows from the datasheet) b8a1a81 5d ago

SI1308EDL-T1-GE3

Vishay Intertech · MOSFETs · SOT-323

SI1308EDL-T1-GE3 from Vishay Intertech, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate terminal; the datasheet limits gate-source voltage to VGS = ±12 V.
2 S passive Source terminal; continuous source-drain diode current is 0.4 A at TC = 25 °C (0.3 A at TA = 25 °C).
3 D passive Drain terminal; drain-source voltage is 30 V (VDS), with continuous drain current of 1.5 A at TA = 25 °C (1.4 A at TC = 25 °C).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SOT-323
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage VDS 30 V VGS = 0 V, ID = 250 μA 2
Gate-Source Threshold Voltage VGS(th) 0.6 1.5 V VDS = VGS, ID = 250 μA 2
Gate-Source Leakage IGSS -20 20 μA VDS = 0 V, VGS = ± 12 V 2
Gate-Source Leakage IGSS 1 μA VDS = 0 V, VGS = 4.5 V 2
Zero Gate Voltage Drain Current IDSS 1 μA VDS = 30 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS 10 μA VDS = 30 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) 2 A VDS ≥ 5 V, VGS = 10 V 2
Drain-Source On-State Resistance RDS(on) 0.11 0.132 Ω VGS = 10 V, ID = 1.4 A 2
Drain-Source On-State Resistance RDS(on) 0.12 0.144 Ω VGS = 4.5 V, ID = 1 A 2
Drain-Source On-State Resistance RDS(on) 0.142 0.185 Ω VGS = 2.5 V, ID = 0.5 A 2
Total Gate Charge Qg 2.7 4.1 nC VDS = 15 V, VGS = 10 V, ID = 1.4 A 2
Total Gate Charge Qg 1.4 2.1 nC VDS = 15 V, VGS = 4.5 V, ID = 1.4 A 2
Gate Resistance Rg 1.4 7 14 Ω f = 1 MHz 2
Rise Time tr 9 18 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 10 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 8 16 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 10 V, Rg = 1 Ω 2
Fall Time tf 8 16 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 10 V, Rg = 1 Ω 2
Turn-On Delay Time td(on) 8 16 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 4.5 V, Rg = 1 Ω 2
Rise Time tr 13 20 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 4.5 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 15 23 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 4.5 V, Rg = 1 Ω 2
Fall Time tf 6 12 ns VDD = 15 V, RL = 13.6 Ω, ID ≅ 1.1 A, VGEN = 4.5 V, Rg = 1 Ω 2
Continuous Source-Drain Diode Current IS 0.4 A TC = 25 °C 2
Pulse Diode Forward Current ISM 6 A 2
Body Diode Voltage VSD 0.8 1.2 V IF = 1.1 A 2
Body Diode Reverse Recovery Time trr 8 16 ns IF = 1.1 A, dI/dt = 100 A/μs, TJ = 25 °C 2
Body Diode Reverse Recovery Charge Qrr 3 6 nC 2
Drain-Source Voltage VDS 30 V 1
Gate-Source Voltage VGS -12 12 V 1
Continuous Drain Current ID 1.4 A TJ = 150 °C, TC = 25 °C 1
Continuous Drain Current ID 1.1 A TJ = 150 °C, TC = 70 °C 1
Continuous Drain Current ID 1.5 A TJ = 150 °C, TA = 25 °C (a, b) 1
Continuous Drain Current ID 1.2 A TJ = 150 °C, TA = 70 °C (a, b) 1
Pulsed Drain Current IDM 6 A t = 300 μs 1
Continuous Source-Drain Diode Current IS 0.4 A TC = 25 °C 1
Continuous Source-Drain Diode Current IS 0.3 A TA = 25 °C 1
Maximum Power Dissipation PD 0.5 W TC = 25 °C 1
Maximum Power Dissipation PD 0.3 W TC = 70 °C 1
Maximum Power Dissipation PD 0.4 W TA = 25 °C (a, b) 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Soldering Recommendations (Peak Temperature) 260 °C 1
Maximum Junction-to-Ambient RthJA 250 300 °C/W t ≤ 10 s 1
Maximum Junction-to-Foot (Drain) RthJF 225 270 °C/W Steady State 1

CAD (KiCad official)

  • Symbol: SI1308EDL-T1-GE3
  • Footprint: Package_TO_SOT_SMD:SOT-323_SC-70
  • 3D model: SOT-323 (KiCad packages3D, STEP)
  • 3D model files: si1308edl-t1-ge3-etched.step / si1308edl-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si1308edl-t1-ge3.step / si1308edl-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (11 pp, sha256 541ab612c7f0f2a7, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF