component
sgm6130yps8g
Public Made by Adomby adom
SGMICRO DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSGM6130YPS8G
SGMICRO · DC-DC Converters · SOIC-8-EP
SGM6130YPS8G from SGMICRO, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | input | High-side gate drive boost input. Supplies the bootstrap voltage for the internal high-side N-channel MOSFET. Connect a 10nF (or greater) capacitor from SW to BS; a 10Ω series resistor between SW and the BS cap is strongly recommended to reduce SW spike voltage. |
| 2 | IN | power_in | Power input. Supplies the IC and the step-down converter switch. Drive with a 4.5V to 28.5V source and bypass to GND with a sufficiently large (e.g. 22µF ceramic) capacitor. |
| 3 | SW | power_out | Power switching output. Switching node that supplies power to the output LC filter. Also serves as the reference for the BS bootstrap capacitor. |
| 4 | GND | power_in | Ground return for the IC. The exposed pad on the backside of the package must be connected to pin 4 and to the GND plane. |
| 5 | FB | input | Feedback input. Regulated to an internal 0.8V reference. Connect to a resistor divider between the output and GND to program the output voltage (VOUT = 0.8V × (1 + R2/R3)). |
| 6 | COMP | output | Loop compensation node. Connect a series RC network from COMP to GND to compensate the regulation control loop; in some cases an additional shunt capacitor from COMP to GND is required. |
| 7 | EN | input | Enable digital input. Drive high to turn the regulator on, drive low to turn it off (output is discharged when off). Leave unconnected for automatic start-up. Absolute maximum -0.3V to 6V. |
| 8 | SS | input | Soft-start control input. Connect a capacitor from SS to GND to program the soft-start period; a 0.1µF capacitor sets ~10ms. Leave unconnected to disable the external soft-start (internal soft-start still active). |
| 9 | EP | power_in | Exposed thermal pad on backside of package. Power ground; must be connected to pin 4 and to the GND plane for proper electrical operation and heat dissipation (θJA ≈ 50°C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SGMICRO |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
SGM6130YPS8G/TR
CAD (KiCad official)
- Symbol:
SGM6130YPS8G - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
sgm6130yps8g-etched.step/sgm6130yps8g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sgm6130yps8g.step/sgm6130yps8g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SGMICRO datasheet (None pp, sha256
75f0cbe078531a5a, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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