component
SGM2049XTRL20G
Public Made by Adomby adom
SGMICRO Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TQFN-20L(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SGM2049XTRL20G
SGMICRO · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TQFN-20L(3.5x3.5)
SGM2049XTRL20G from SGMICRO, in a TQFN-20L(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; use an output capacitor with effective capacitance of 10μF to 1000μF placed as close as possible to the OUT pin to ensure stability. |
| 2 | SNS | input | Output voltage sense input, connected to the load side of the output trace only when pin-selectable programming is used; keep floating when VOUT is set by external resistors. |
| 3 | FB | input | Feedback voltage input connected to the midpoint of the external resistor divider that sets the output voltage; resistors should be placed as close as possible to this pin. |
| 4 | PG | output | Open-drain, active-high power-good output indicating VOUT status, going high impedance when VOUT reaches VIT(PG) of the target; PG sink current is limited to 5mA and a 10kΩ to 100kΩ pull-up is recommended. |
| 5 | 50mV | input | Output voltage setting pin that adds 50mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 6 | 100mV | input | Output voltage setting pin that adds 100mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 7 | 200mV | input | Output voltage setting pin that adds 200mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 8 | GND | power_in | Ground pin. |
| 9 | 400mV | input | Output voltage setting pin that adds 400mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 10 | 800mV | input | Output voltage setting pin that adds 800mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 11 | 1.6V | input | Output voltage setting pin that adds 1.6V to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 12 | BIAS | power_in | Bias supply pin for internal control circuits, monitored by internal UVLO; bias is required when VIN < 1.4V, with a bias supply voltage range of 3V to 7V. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin; an external capacitor CNR/SS to GND reduces output noise and slows the VOUT rise, with the pin voltage limited to 3.6V absolute maximum. |
| 14 | EN | input | Enable pin: driving EN high turns the regulator on and driving it low turns it off, with VIL(EN) of 0 to 0.5V and VIH(EN) of 1.1V to 7V; it must be tied to IN or BIAS if enable is not used. |
| 15 | IN | power_in | Input supply voltage pin with an operating range of 1.1V to 7V; a 10μF or larger ceramic capacitor from IN to GND is recommended and should be placed close to the pin. |
| 16 | IN | power_in | Input supply voltage pin with an operating range of 1.1V to 7V; a 10μF or larger ceramic capacitor from IN to GND is recommended and should be placed close to the pin. |
| 17 | IN | power_in | Input supply voltage pin with an operating range of 1.1V to 7V; a 10μF or larger ceramic capacitor from IN to GND is recommended and should be placed close to the pin. |
| 18 | GND | power_in | Ground pin. |
| 19 | OUT | power_out | Regulator output; use an output capacitor with effective capacitance of 10μF to 1000μF placed as close as possible to the OUT pin to ensure stability. |
| 20 | OUT | power_out | Regulator output; use an output capacitor with effective capacitance of 10μF to 1000μF placed as close as possible to the OUT pin to ensure stability. |
| 21 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SGMICRO |
| Package | TQFN-20L(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage Range | VIN | 1.1 | 7 | V | 4 | ||
| Bias Supply Voltage Range | VBIAS | 3 | 7 | V | VIN = 1.1V | 4 | |
| Output Voltage Range (pin-selectable operation) | VOUT | 0.8 | 3.95 | V | Pin-selectable operation | 4 | |
| Output Voltage Range (adjustable operation) | VOUT | 0.8 | 5.2 | V | Adjustable operation, using external resistors | 4 | |
| Feedback Voltage | VFB | 0.792 | 0.8 | 0.808 | V | TJ = +25℃ | 4 |
| Feedback Voltage (full junction temperature range) | VFB | 0.784 | 0.816 | V | TJ = -40℃ to +125℃ | 4 | |
| Input Supply UVLO with Bias (VIN rising) | VUVLO1(IN) | 0.78 | 0.95 | V | VIN rising with VBIAS = 3V | 4 | |
| Input Supply UVLO without Bias (VIN rising) | VUVLO2(IN) | 1.14 | 1.4 | V | VIN rising | 4 | |
| Bias Supply UVLO (VBIAS rising) | VUVLO(BIAS) | 2.5 | 2.8 | V | VBIAS rising, VIN = 1.1V | 4 | |
| Output Voltage Accuracy (TJ = +25℃) | VOUT | -1 | 1 | % | VIN = 1.4V to 7V without BIAS, or VIN = 1.1V, VBIAS = 3V to 7V, IOUT = 5mA to 2A, TJ = +25℃ | 4 | |
| Output Voltage Accuracy (TJ = -40℃ to +125℃) | VOUT | -1.7 | 1.3 | % | VIN = 1.4V to 7V without BIAS, or VIN = 1.1V, VBIAS = 3V to 7V, IOUT = 5mA to 2A, TJ = -40℃ to +125℃ | 4 | |
| Output Voltage Accuracy, pin-selectable (TJ = +25℃) | VOUT | -1.4 | 1.4 | % | Pin-selectable operation, IOUT = 5mA, TJ = +25℃ | 4 | |
| Output Voltage Accuracy, pin-selectable (TJ = -40℃ to +125℃) | VOUT | -2 | 2 | % | Pin-selectable operation, IOUT = 5mA, TJ = -40℃ to +125℃ | 4 | |
| Line Regulation | ΔVOUT/ΔVIN | 0.04 | 1.5 | mV/V | VIN = 1.4V to 7V, IOUT = 5mA | 4 | |
| Load Regulation | ΔVOUT/ΔIOUT | 0.1 | 1.8 | mV/A | VBIAS = 3V to 7V, VIN = 1.1V, IOUT = 5mA to 2A | 4 | |
| Load Regulation | ΔVOUT/ΔIOUT | 0.1 | 2.2 | mV/A | IOUT = 5mA to 2A | 4 | |
| Load Regulation (VOUT = 5.2V) | ΔVOUT/ΔIOUT | 0.7 | 4.5 | mV/A | IOUT = 5mA to 2A, VOUT = 5.2V | 4 | |
| Dropout Voltage | VDROP | 75 | 120 | mV | VIN = 1.4V, IOUT = 2A, VFB = 0.776V | 4 | |
| Output Current Limit | ILIMIT | 2.2 | 3.2 | 4 | A | VOUT forced at 90% × VOUT(NOM), VIN = VOUT(NOM) + 0.4V | 4 |
| GND Pin Current | IGND | 3.3 | 4.1 | mA | VIN = 7V, IOUT = 5mA | 4 | |
| GND Pin Current | IGND | 2.3 | 3 | mA | VIN = 1.4V, IOUT = 2A | 4 | |
| Shutdown Current | ISHDN | 1.4 | 3 | µA | PG = Open, VIN = 7V, VEN = 0.5V, TJ = +25℃ | 4 | |
| BIAS Pin Current | IBIAS | 2.9 | 3.6 | mA | VIN = 1.1V, VBIAS = 7V, VOUT(NOM) = 0.8V, IOUT = 2A | 4 | |
| EN Pin Low-Level Input Voltage | VIL(EN) | 0 | 0.5 | V | EN input voltage “L” | 4 | |
| EN Pin High-Level Input Voltage | VIH(EN) | 1.1 | 7 | V | EN input voltage “H” | 4 | |
| EN Pin Current | IEN | -0.3 | 0.3 | µA | VIN = 7V, VEN = 0V and 7V | 4 | |
| Output Discharge Resistance | RDIS | 190 | 260 | 330 | Ω | VIN = 1.4V, VEN = 0V, VOUT = 0.5V | 4 |
| PG Pin Threshold (falling VOUT) | VIT(PG) | 84 | 89 | 93 | % × VOUT | For falling VOUT | 5 |
| PG Pin Low-Level Output Voltage | VOL(PG) | 0.17 | 0.3 | V | VOUT < VIT(PG), IPG = -1mA (current into device) | 5 | |
| PG Pin Leakage Current | Ilkg(PG) | 0.01 | 0.5 | µA | VOUT > VIT(PG), VPG = 7V, VIN = 7V | 5 | |
| NR/SS Pin Charging Current | INR/SS | 3.5 | 5.8 | 8.5 | µA | VNR/SS = GND, VIN = 7V | 5 |
| FB Pin Leakage Current | IFB | -120 | 120 | nA | VIN = 7V | 5 | |
| Bias Supply Voltage Range (recommended) | 3 | 7 | V | Note 1: required when VIN < 1.4V | 2 | ||
| Enable Voltage Range | 0 | V | Upper limit printed as VIN | 2 | |||
| Output Current | IOUT | 0 | 2 | A | 2 | ||
| Input Effective Capacitance | CIN | 5 | µF | MIN as printed | 2 | ||
| Output Effective Capacitance | COUT | 10 | 1000 | µF | 2 | ||
| Bias Effective Capacitance | CBIAS | 5 | µF | MIN as printed | 2 | ||
| Power-Good Pull-Up Resistance | 10 | 100 | kΩ | 2 | |||
| Operating Junction Temperature Range | TJ | -40 | 125 | ℃ | 2 | ||
| IN, BIAS, PG, EN to GND | -0.3 | 8 | V | 2 | |||
| SNS, OUT to GND | -0.3 | V | Upper limit printed as Min(VIN + 0.3V, 8V) | 2 | |||
| NR/SS, FB to GND | -0.3 | 3.6 | V | 2 | |||
| 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V to GND | -0.3 | V | Upper limit printed as VOUT + 0.3V | 2 | |||
| PG Current (sink current into device) | 5 | mA | Sink current into device | 2 | |||
| Junction Temperature | TJ | 150 | ℃ | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | ℃ | 2 | ||
| Lead Temperature (soldering) | 260 | ℃ | Soldering, 10s | 2 | |||
| ESD Susceptibility CDM | 1000 | V | CDM | 2 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 40 | ℃/W | TQFN-3.5×3.5-20L | 2 | ||
| Package Thermal Resistance, junction-to-board | θJB | 14 | ℃/W | TQFN-3.5×3.5-20L | 2 | ||
| Package Thermal Resistance, junction-to-case | θJC | 29 | ℃/W | TQFN-3.5×3.5-20L | 2 |
CAD (KiCad official)
- Symbol:
SGM2049XTRL20G - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: TQFN-20L(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sgm2049xtrl20g-etched.step/sgm2049xtrl20g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sgm2049xtrl20g.step/sgm2049xtrl20g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SGMICRO datasheet (18 pp, sha256
1acf47b87f998ace, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SGM2049XTRL20G
**SGMICRO** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TQFN-20L(3.5x3.5)
SGM2049XTRL20G from SGMICRO, in a TQFN-20L(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; use an output capacitor with effective capacitance of 10μF to 1000μF placed as close as possible to the OUT pin to ensure stability. |
| 2 | SNS | input | Output voltage sense input, connected to the load side of the output trace only when pin-selectable programming is used; keep floating when VOUT is set by external resistors. |
| 3 | FB | input | Feedback voltage input connected to the midpoint of the external resistor divider that sets the output voltage; resistors should be placed as close as possible to this pin. |
| 4 | PG | output | Open-drain, active-high power-good output indicating VOUT status, going high impedance when VOUT reaches VIT(PG) of the target; PG sink current is limited to 5mA and a 10kΩ to 100kΩ pull-up is recommended. |
| 5 | 50mV | input | Output voltage setting pin that adds 50mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 6 | 100mV | input | Output voltage setting pin that adds 100mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 7 | 200mV | input | Output voltage setting pin that adds 200mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 8 | GND | power_in | Ground pin. |
| 9 | 400mV | input | Output voltage setting pin that adds 400mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 10 | 800mV | input | Output voltage setting pin that adds 800mV to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 11 | 1.6V | input | Output voltage setting pin that adds 1.6V to the output when connected to GND; leave open when VOUT is set by an external resistor divider. |
| 12 | BIAS | power_in | Bias supply pin for internal control circuits, monitored by internal UVLO; bias is required when VIN < 1.4V, with a bias supply voltage range of 3V to 7V. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin; an external capacitor CNR/SS to GND reduces output noise and slows the VOUT rise, with the pin voltage limited to 3.6V absolute maximum. |
| 14 | EN | input | Enable pin: driving EN high turns the regulator on and driving it low turns it off, with VIL(EN) of 0 to 0.5V and VIH(EN) of 1.1V to 7V; it must be tied to IN or BIAS if enable is not used. |
| 15 | IN | power_in | Input supply voltage pin with an operating range of 1.1V to 7V; a 10μF or larger ceramic capacitor from IN to GND is recommended and should be placed close to the pin. |
| 16 | IN | power_in | Input supply voltage pin with an operating range of 1.1V to 7V; a 10μF or larger ceramic capacitor from IN to GND is recommended and should be placed close to the pin. |
| 17 | IN | power_in | Input supply voltage pin with an operating range of 1.1V to 7V; a 10μF or larger ceramic capacitor from IN to GND is recommended and should be placed close to the pin. |
| 18 | GND | power_in | Ground pin. |
| 19 | OUT | power_out | Regulator output; use an output capacitor with effective capacitance of 10μF to 1000μF placed as close as possible to the OUT pin to ensure stability. |
| 20 | OUT | power_out | Regulator output; use an output capacitor with effective capacitance of 10μF to 1000μF placed as close as possible to the OUT pin to ensure stability. |
| 21 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SGMICRO |
| Package | TQFN-20L(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage Range | VIN | 1.1 | | 7 | V | | 4 |
| Bias Supply Voltage Range | VBIAS | 3 | | 7 | V | VIN = 1.1V | 4 |
| Output Voltage Range (pin-selectable operation) | VOUT | 0.8 | | 3.95 | V | Pin-selectable operation | 4 |
| Output Voltage Range (adjustable operation) | VOUT | 0.8 | | 5.2 | V | Adjustable operation, using external resistors | 4 |
| Feedback Voltage | VFB | 0.792 | 0.8 | 0.808 | V | TJ = +25℃ | 4 |
| Feedback Voltage (full junction temperature range) | VFB | 0.784 | | 0.816 | V | TJ = -40℃ to +125℃ | 4 |
| Input Supply UVLO with Bias (VIN rising) | VUVLO1(IN) | 0.78 | | 0.95 | V | VIN rising with VBIAS = 3V | 4 |
| Input Supply UVLO without Bias (VIN rising) | VUVLO2(IN) | 1.14 | | 1.4 | V | VIN rising | 4 |
| Bias Supply UVLO (VBIAS rising) | VUVLO(BIAS) | 2.5 | | 2.8 | V | VBIAS rising, VIN = 1.1V | 4 |
| Output Voltage Accuracy (TJ = +25℃) | VOUT | -1 | | 1 | % | VIN = 1.4V to 7V without BIAS, or VIN = 1.1V, VBIAS = 3V to 7V, IOUT = 5mA to 2A, TJ = +25℃ | 4 |
| Output Voltage Accuracy (TJ = -40℃ to +125℃) | VOUT | -1.7 | | 1.3 | % | VIN = 1.4V to 7V without BIAS, or VIN = 1.1V, VBIAS = 3V to 7V, IOUT = 5mA to 2A, TJ = -40℃ to +125℃ | 4 |
| Output Voltage Accuracy, pin-selectable (TJ = +25℃) | VOUT | -1.4 | | 1.4 | % | Pin-selectable operation, IOUT = 5mA, TJ = +25℃ | 4 |
| Output Voltage Accuracy, pin-selectable (TJ = -40℃ to +125℃) | VOUT | -2 | | 2 | % | Pin-selectable operation, IOUT = 5mA, TJ = -40℃ to +125℃ | 4 |
| Line Regulation | ΔVOUT/ΔVIN | | 0.04 | 1.5 | mV/V | VIN = 1.4V to 7V, IOUT = 5mA | 4 |
| Load Regulation | ΔVOUT/ΔIOUT | | 0.1 | 1.8 | mV/A | VBIAS = 3V to 7V, VIN = 1.1V, IOUT = 5mA to 2A | 4 |
| Load Regulation | ΔVOUT/ΔIOUT | | 0.1 | 2.2 | mV/A | IOUT = 5mA to 2A | 4 |
| Load Regulation (VOUT = 5.2V) | ΔVOUT/ΔIOUT | | 0.7 | 4.5 | mV/A | IOUT = 5mA to 2A, VOUT = 5.2V | 4 |
| Dropout Voltage | VDROP | | 75 | 120 | mV | VIN = 1.4V, IOUT = 2A, VFB = 0.776V | 4 |
| Output Current Limit | ILIMIT | 2.2 | 3.2 | 4 | A | VOUT forced at 90% × VOUT(NOM), VIN = VOUT(NOM) + 0.4V | 4 |
| GND Pin Current | IGND | | 3.3 | 4.1 | mA | VIN = 7V, IOUT = 5mA | 4 |
| GND Pin Current | IGND | | 2.3 | 3 | mA | VIN = 1.4V, IOUT = 2A | 4 |
| Shutdown Current | ISHDN | | 1.4 | 3 | µA | PG = Open, VIN = 7V, VEN = 0.5V, TJ = +25℃ | 4 |
| BIAS Pin Current | IBIAS | | 2.9 | 3.6 | mA | VIN = 1.1V, VBIAS = 7V, VOUT(NOM) = 0.8V, IOUT = 2A | 4 |
| EN Pin Low-Level Input Voltage | VIL(EN) | 0 | | 0.5 | V | EN input voltage “L” | 4 |
| EN Pin High-Level Input Voltage | VIH(EN) | 1.1 | | 7 | V | EN input voltage “H” | 4 |
| EN Pin Current | IEN | -0.3 | | 0.3 | µA | VIN = 7V, VEN = 0V and 7V | 4 |
| Output Discharge Resistance | RDIS | 190 | 260 | 330 | Ω | VIN = 1.4V, VEN = 0V, VOUT = 0.5V | 4 |
| PG Pin Threshold (falling VOUT) | VIT(PG) | 84 | 89 | 93 | % × VOUT | For falling VOUT | 5 |
| PG Pin Low-Level Output Voltage | VOL(PG) | | 0.17 | 0.3 | V | VOUT < VIT(PG), IPG = -1mA (current into device) | 5 |
| PG Pin Leakage Current | Ilkg(PG) | | 0.01 | 0.5 | µA | VOUT > VIT(PG), VPG = 7V, VIN = 7V | 5 |
| NR/SS Pin Charging Current | INR/SS | 3.5 | 5.8 | 8.5 | µA | VNR/SS = GND, VIN = 7V | 5 |
| FB Pin Leakage Current | IFB | -120 | | 120 | nA | VIN = 7V | 5 |
| Bias Supply Voltage Range (recommended) | | 3 | | 7 | V | Note 1: required when VIN < 1.4V | 2 |
| Enable Voltage Range | | 0 | | | V | Upper limit printed as VIN | 2 |
| Output Current | IOUT | 0 | | 2 | A | | 2 |
| Input Effective Capacitance | CIN | 5 | | | µF | MIN as printed | 2 |
| Output Effective Capacitance | COUT | 10 | | 1000 | µF | | 2 |
| Bias Effective Capacitance | CBIAS | 5 | | | µF | MIN as printed | 2 |
| Power-Good Pull-Up Resistance | | 10 | | 100 | kΩ | | 2 |
| Operating Junction Temperature Range | TJ | -40 | | 125 | ℃ | | 2 |
| IN, BIAS, PG, EN to GND | | -0.3 | | 8 | V | | 2 |
| SNS, OUT to GND | | -0.3 | | | V | Upper limit printed as Min(VIN + 0.3V, 8V) | 2 |
| NR/SS, FB to GND | | -0.3 | | 3.6 | V | | 2 |
| 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V to GND | | -0.3 | | | V | Upper limit printed as VOUT + 0.3V | 2 |
| PG Current (sink current into device) | | | | 5 | mA | Sink current into device | 2 |
| Junction Temperature | TJ | | | 150 | ℃ | | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | ℃ | | 2 |
| Lead Temperature (soldering) | | | | 260 | ℃ | Soldering, 10s | 2 |
| ESD Susceptibility CDM | | | | 1000 | V | CDM | 2 |
| Package Thermal Resistance, junction-to-ambient | θJA | | 40 | | ℃/W | TQFN-3.5×3.5-20L | 2 |
| Package Thermal Resistance, junction-to-board | θJB | | 14 | | ℃/W | TQFN-3.5×3.5-20L | 2 |
| Package Thermal Resistance, junction-to-case | θJC | | 29 | | ℃/W | TQFN-3.5×3.5-20L | 2 |
## CAD (KiCad official)
- Symbol: `SGM2049XTRL20G`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm`
- 3D model: TQFN-20L(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `sgm2049xtrl20g-etched.step` / `sgm2049xtrl20g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sgm2049xtrl20g.step` / `sgm2049xtrl20g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SGMICRO datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589837100746113024) (18 pp, sha256 `1acf47b87f998ace`, retrieved 2026-10-13, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sgm2049xtrl20g-datasheet.pdf)