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Contents

README

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SG3525ADTR

XBLW · AC-DC Controllers And Regulators · SOP-16

SG3525ADTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Inv. Input input Inverting input of the error amplifier, whose common-mode range includes the reference voltage.
2 Noninv. Input input Noninverting input of the error amplifier, whose common-mode range includes the reference voltage.
3 Sync input Oscillator sync input, allowing multiple units to be slaved or a single unit to be synchronized to an external system clock.
4 OSC. Output output Oscillator output.
5 CT passive Oscillator timing capacitor connection; recommended 0.001 to 0.2 uF.
6 RT passive Oscillator timing resistor connection; recommended 2.0 to 150 kOhm.
7 Discharge passive Oscillator discharge pin; a single deadtime resistor (0 to 500 Ohm recommended) is connected between CT and Discharge.
8 Soft-Start passive Soft-start pin requiring only an external timing capacitor.
9 Compensation bidirectional Error amplifier output / compensation node feeding the PWM comparator.
10 Shutdown input Shutdown input controlling both the soft-start circuitry and the output stages, giving instantaneous turn-off through the PWM latch.
11 Output A output Totem-pole output A capable of sinking and sourcing in excess of 150 mA, with NOR logic giving a low output in the off-state.
12 Ground power_in Ground connection.
13 VC power_in Collector supply voltage for the output stage; recommended 4.5 to 35 V, 40 V maximum.
14 Output B output Totem-pole output B capable of sinking and sourcing in excess of 150 mA, with NOR logic giving a low output in the off-state.
15 VCC power_in Supply voltage input; recommended 8.0 to 35 V, 40 V maximum.
16 Vref power_out On-chip +5.1 V reference trimmed to ±1%; reference load current 0 to 20 mA recommended.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: SG3525ADTR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: sg3525adtr-etched.step / sg3525adtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sg3525adtr.step / sg3525adtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (9 pp, sha256 0cd194f4be5d3f44, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF