# SE30P12

**SINO IC** · MOSFETs · SOP-8

SE30P12 from SINO IC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET; VDS rating is -30V and continuous drain current is -11A. |
| 2 | S | passive | Source of the P-channel MOSFET, tied with the other source pins; VGS rating is ±20V. |
| 3 | S | passive | Source of the P-channel MOSFET, tied with the other source pins. |
| 4 | G | input | Gate of the P-channel MOSFET; VGS maximum ±20V, threshold -1 to -3V at ID=-250µA. |
| 5 | D | passive | Drain of the P-channel MOSFET; VDS = -30V, pulsed drain current -50A. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied with the other drain pins. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied with the other drain pins. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied with the other drain pins. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | SINO IC |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | -30 | V |  | 1 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Drain Current, Continuous | ID |  |  | -11 | A | Continuous | 1 |
| Drain Current, Pulsed | ID |  |  | -50 | A | Pulsed | 1 |
| Total Power Dissipation | PD |  |  | 2 | W | @TA=25℃ | 1 |
| Operating Junction Temperature Range | TJ | -55 |  | 150 | ℃ |  | 1 |
| Drain-Source Breakdown Voltage | BVDSS | -30 | -33 |  | V | ID=-250μA, VGS=0 | 2 |
| Drain to Source Leakage Current | IDSS |  |  | -5 | μA | VDS= -24V, VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS |  |  | 100 | nA | VGS= 20V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 | -1.5 | -3 | V | VDS=VGS, ID=-250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 11.5 | 15 | mΩ | VGS=-10V, ID=-10A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 18 | 25 | mΩ | VGS=-4.5V, ID=-7A | 2 |
| Junction to Ambient (t≦10s) | RθJA |  | 26 | 40 | ℃/W | t≦10s | 2 |

## CAD (KiCad official)

- Symbol: `SE30P12`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `se30p12-etched.step` / `se30p12-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `se30p12.step` / `se30p12.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [SINO IC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588902292417994752) (5 pp, sha256 `4e4c312c36313f7f`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/se30p12-datasheet.pdf)