# SD2017B

**Hangzhou SDIC Microelectronics** · Interface - Specialized · LQFP-32(7x7)

SD2017B from Hangzhou SDIC Microelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TEST5 | passive | Must be connected to VSS. |
| 2 | INRESET | input | Chip reset input, active low. |
| 3 | IAREF_ENb | input | Reference enable: low enables the internal 1.5V reference and buffer; high disables them and requires an external 2.5V buffered reference on the REF pin. |
| 4 | TEST8 | passive | Must be connected to VSS. |
| 5 | TEST9 | passive | Must be connected to VSS. |
| 6 | VSS | power_in | Digital ground, must be at the same voltage as VSSA. |
| 7 | OTXA | output | HART FSK signal output, connected to the 4-20 mA current loop; drive amplitude 0.5V to 1.0V with 4.7nF to 68nF capacitive load range. |
| 8 | IAREF | output | Internal 1.5V reference voltage output, to be decoupled with a 1µF capacitor to VSSA. |
| 9 | NC | unconnected | Leave floating or connect to VSS. |
| 10 | OCBIAS | output | Sets the bias current; bias resistor RBIAS connects between this pin and VSSA, recommended 330kΩ. |
| 11 | TEST10 | passive | Leave floating or connect to VSS. |
| 12 | VSSA | power_in | Analog ground, must be at the same voltage as VSS. |
| 13 | VDDA | power_in | Analog supply, must be at the same voltage as VDD; operating range 2.7V to 5.5V. |
| 14 | IRXA | input | HART FSK signal input from the 4-20 mA current loop port, input range 0 to 1.5V. |
| 15 | NC | unconnected | Leave floating or connect to VSS. |
| 16 | NC | unconnected | Leave floating or connect to VSS. |
| 17 | OXTL | output | Crystal oscillator output; external 3.6864MHz clock input when using CMOS clock. |
| 18 | IXTL | input | Crystal oscillator input; tied to VSS when an external CMOS clock is used. |
| 19 | VSSA | power_in | Analog ground, must be at the same voltage as VSS. |
| 20 | VSS | power_in | Digital ground, must be at the same voltage as VSSA. |
| 21 | VDD | power_in | Digital supply, must be at the same voltage as VDDA. |
| 22 | INRTS | input | Request to send input, active low: low selects transmit mode, high selects receive mode. |
| 23 | ITXD | input | Transmit data input to the modulator, modulated and sent out via OTXA. |
| 24 | TEST11 | passive | Leave floating or connect to VSS. |
| 25 | ORXD | output | Demodulated HART data output to the external UART interface. |
| 26 | OCD | output | Carrier detect output, high when a valid carrier is present on IRXA. |
| 27 | TEST12 | passive | Leave floating or connect to VSS. |
| 28 | TEST1 | passive | Leave floating or connect to VSS. |
| 29 | TEST2 | passive | Leave floating or connect to VSS. |
| 30 | VDD | power_in | Digital supply, must be at the same voltage as VDDA. |
| 31 | TEST3 | passive | Leave floating or connect to VSS. |
| 32 | TEST4 | passive | Leave floating or connect to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Hangzhou SDIC Microelectronics |
| Package | LQFP-32(7x7) |
| Category | Interface ICs |
| Pins | 32 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 工作温度 | TA | -55 |  | 125 | ℃ |  | 7 |
| 储存温度 | TS | -65 |  | 150 | ℃ |  | 7 |
| 供电电压 | VDDA，VDD | -0.3 |  | 7 | V |  | 7 |
| 人体模型ESD |  |  |  | 4000 | V | 人体模型 | 7 |
| 机械模型ESD |  |  |  | 400 | V | 机械模型 | 7 |
| 电源电压 | VDDA，VDD | 2.7 | 3.3 | 5.5 | V |  | 7 |
| 功耗 解调模式 | IDD |  | 97 | 135 | μA | 外部时钟、-55℃至+85℃ | 7 |
| 功耗 解调模式 | IDD |  |  | 140 | μA | 外部时钟、-55℃至+125℃ | 7 |
| 功耗 解调模式 | IDD |  | 150 | 220 | μA | 外部晶振、-55℃至+85℃ | 7 |
| 功耗 解调模式 | IDD |  |  | 240 | μA | 外部晶振、-55℃至+125℃ | 7 |
| 功耗 调制模式 | IDD |  | 67 | 85 | μA | 外部时钟、-55℃至+85℃ | 7 |
| 功耗 调制模式 | IDD |  |  | 90 | μA | 外部时钟、-55℃至+125℃ | 7 |
| 功耗 调制模式 | IDD |  | 112 | 175 | μA | 外部晶振、-55℃至+85℃ | 7 |
| 功耗 调制模式 | IDD |  |  | 190 | μA | 外部晶振、-55℃至+125℃ | 7 |
| VIAREF 初始精度 | VIAREF | 1.48 | 1.5 | 1.52 | V |  | 7 |
| 负载调整率 |  |  | 1.5 |  | ppm/μA | 利用 500μA 负载测试 | 7 |
| 电压调整率 |  |  | 60 |  | μV/V |  | 7 |
| 偏置电流 | IOCB |  | 4.5 |  | μA |  | 7 |
| 载波有效幅度 |  | 90 | 105 | 115 | mVp-p | OCD位置 | 7 |
| IRXA 输入范围 |  | 0 |  | 1.5 | V |  | 7 |
| OTXA 输出幅度 |  |  | 500 |  | mVp-p |  | 7 |
| 逻辑“1”频率 |  |  | 1200 |  | Hz |  | 7 |
| 逻辑“0”频率 |  |  | 2200 |  | Hz |  | 7 |
| 相位连续性误差 |  |  | 0 |  | 度 |  | 7 |
| 最大阻性负载 | RLOAD |  |  | 160 | Ω | 负载如图 5 所示的 RLOAD | 7 |
| 外部时钟 频率精度 |  | 3.6496 | 3.6864 | 3.7232 | MHz | 外部时钟 | 7 |
| 高电平电流 | IIH | -0.1 |  | 0.1 | μA |  | 7 |
| 低电平电流 | IIL | -0.1 |  | 0.1 | μA |  | 7 |

## CAD (KiCad official)

- Symbol: `SD2017B`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `sd2017b-etched.step` / `sd2017b-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sd2017b.step` / `sd2017b.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Hangzhou SDIC Microelectronics datasheet](docs/sd2017b-datasheet.pdf) (8 pp, sha256 `24a89c7f8b94e019`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sd2017b-datasheet.pdf)