# SCT52242STDR

**SCT** · Gate Drivers · SOP-8

SCT52242STDR from SCT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Channel A enable logic input, TTL compatible; floating logic high, and the driver is disabled when ENA falls below its lower threshold (typically 1.1 V). |
| 2 | INA- | input | Channel A logic input, TTL compatible; floating logic low, with an input voltage range of -5 V to 24 V. |
| 3 | GND | power_in | Power ground; must be soldered directly to the ground plane for thermal performance improvement and electrical contact. |
| 4 | INB- | input | Channel B logic input, TTL compatible; floating logic low, with an input voltage range of -5 V to 24 V. |
| 5 | OUTB | output | Channel B gate driver output, capable of 4 A peak source and sink current. |
| 6 | VDD | power_in | Power supply with an operating range of 4.5 V to 24 V; must be locally bypassed by a ceramic capacitor. |
| 7 | OUTA | output | Channel A gate driver output, capable of 4 A peak source and sink current. |
| 8 | ENB | input | Channel B enable logic input, TTL compatible; floating logic high, and the driver is disabled when ENB falls below its lower threshold (typically 1.1 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | SOP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (ENA, ENB) absolute maximum | ENA, ENB | -0.3 |  | 26 | V |  | 2 |
| Input voltage (INA-, INB-) absolute maximum | INA-, INB- | -5 |  | 26 | V |  | 2 |
| Output voltage (OUTA, OUTB) absolute maximum | OUTA, OUTB | -0.3 |  | 26 | V |  | 2 |
| VDD supply voltage absolute maximum | VDD | -0.3 |  | 26 | V |  | 2 |
| Operating junction temperature absolute maximum | TJ | -40 |  | 150 | °C |  | 2 |
| Storage temperature | TSTG | -65 |  | 150 | °C |  | 2 |
| VDD supply voltage range (recommended) | VDD | 4.5 |  | 24 | V |  | 3 |
| Input voltage range (recommended) | VINA-,INB- | -5 |  | 24 | V |  | 3 |
| Operating junction temperature (recommended) | TJ | -40 |  | 150 | °C |  | 3 |
| Junction to ambient thermal resistance RθJA (SOP-8L) | RθJA |  | 90 |  | °C/W | Reference value, PCB dependent | 3 |
| Junction to case thermal resistance RθJC (SOP-8L) | RθJC |  | 39 |  | °C/W | Reference value, PCB dependent | 3 |
| Operating supply voltage | VDD | 4.5 |  | 24 | V |  | 4 |
| Input UVLO, VDD rising | VDD_UVLO |  | 4.2 | 4.5 | V | VDD rising | 4 |
| UVLO hysteresis | VDD_UVLO |  | 300 |  | mV |  | 4 |
| Supply current | IQ |  | 55 |  | uA | EN=VDD=3.5V, INA- =INB- =GND | 4 |
| Supply current | IQ |  | 120 |  | uA | EN=VDD=12V, INA- =INB- = VDD=12V | 4 |
| Input logic high threshold | VINA-,INB-_H |  | 2.1 | 2.4 | V | Output logic low | 4 |
| Input logic low threshold | VINA-,INB-_L | 0.8 | 1 |  | V | Output logic high | 4 |
| Input threshold hysteresis | VIN_Hys |  | 1.1 |  | V |  | 4 |
| Enable logic high threshold | VENA,ENB_H |  | 2.1 | 2.4 | V |  | 4 |
| Enable logic low threshold | VENA,ENB_L | 0.8 |  | 1 | V |  | 4 |
| Enable threshold hysteresis | VEN_Hys |  | 1.1 |  | V |  | 4 |
| Output high voltage (VDD - VOUT) | VDD_VOH |  | 150 |  | mV | IOUT= - 10mA | 4 |
| Output low voltage | VOL |  | 10 |  | mV | IOUT= 10mA | 4 |
| Output sink/source peak current | ISINK/SRC |  | 4 |  | A | CLoad=10nF, FSW=1kHz | 4 |
| Output pull-high resistance (PMOS on) | ROH |  | 9 |  | Ω | IOUT= - 10mA | 4 |
| Output pull-low resistance | ROL |  | 0.6 |  | Ω | IOUT= 10mA | 4 |
| Output rising time | TR |  | 8 | 20 | ns | CLoad=1nF | 4 |
| Output falling time | TF |  | 8 | 20 | ns | CLoad=1nF | 4 |
| Input to output propagation delay, rising edge | TD_IN |  | 13 | 25 | ns |  | 4 |
| Input to output propagation delay, falling edge | TD_IN |  | 13 | 25 | ns |  | 4 |
| Input to output delay matching | TM_IN |  | 1 | 4 | ns |  | 4 |
| Minimum input pulse width | TMIN_ON |  | 20 | 30 | ns | CLoad=1nF | 4 |
| Thermal shutdown threshold | TSD |  | 170 |  | °C | TJ rising | 4 |
| Thermal shutdown hysteresis | TSD |  | 25 |  | °C |  | 4 |

## CAD (KiCad official)

- Symbol: `SCT52242STDR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sct52242stdr-etched.step` / `sct52242stdr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sct52242stdr.step` / `sct52242stdr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [SCT datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918362008772608) (19 pp, sha256 `f2853d6b825cc80a`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sct52242stdr-datasheet.pdf)