component
SCT51240TWBR
Public Made by Adomby adom
SCT Gate Drivers, TSOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SCT51240TWBR
SCT · Gate Drivers · TSOT-23-5L
SCT51240TWBR from SCT, in a TSOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Gate driver supply, must be decoupled by a ceramic capacitor (0.1 µF plus 1 µF or 10 µF recommended), with an operating supply range of 4.5 V to 24 V. |
| 2 | GND | power_in | Power ground, which must be soldered directly to ground planes for improved thermal performance and electrical contact. |
| 3 | IN+ | input | Non-inverting TTL-compatible logic input that floats low; it carries the PWM signal in non-inverting operation and is connected to VDD in inverting operation. |
| 4 | IN- | input | Inverting TTL-compatible logic input that floats low; it carries the PWM signal in inverting operation and is connected to GND in non-inverting operation. |
| 5 | OUT | output | Gate driver output, rail-to-rail, capable of 4 A peak source and 4 A peak sink current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | TSOT-23-5L |
| Category | Motor Driver ICs |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage | VDD | 4.5 | 24 | V | 4 | ||
| Input UVLO, VDD rising | VDD_UVLO | 4.2 | 4.5 | V | VDD rising | 4 | |
| Input UVLO hysteresis | 300 | mV | 4 | ||||
| Quiescent current | IQ | 38 | uA | IN+=IN-=GND, VDD=3.5V | 4 | ||
| Quiescent current | IQ | 120 | uA | IN+=IN-=GND, VDD=12V | 4 | ||
| Input+ logic high threshold | VIN+ | 2.1 | 2.4 | V | 4 | ||
| Input+ logic low threshold | VIN+ | 0.8 | 1 | V | 4 | ||
| Input+ hysteresis | VIN+_Hys | 1.1 | V | 4 | |||
| Input- logic high threshold | VIN-_H | 2.1 | 2.4 | V | 4 | ||
| Input- logic low threshold | VIN-_L | 0.8 | 1 | V | 4 | ||
| Input- hysteresis | VIN-_Hys | 1.1 | V | 4 | |||
| Output High Voltage (only PMOS ON) | VDD_VOH | 150 | mV | IOUT=10mA | 4 | ||
| Output Low Voltage | VOL | 10 | mV | IOUT=10mA | 4 | ||
| Output sink/source peak current | ISINK/SRC | 4 | A | CLoad=10nF, Fsw=1kHz | 4 | ||
| Output pull high resistance (only PMOS ON) | ROH | 8.5 | Ω | IOUT= - 10mA | 4 | ||
| Output pull low resistance | ROL | 0.6 | Ω | IOUT= 10mA | 4 | ||
| Output rising time | TR | 9 | 20 | ns | CLoad=1nF | 4 | |
| Output falling time | TF | 6 | 20 | ns | CLoad=1nF | 4 | |
| IN+ to output propagation delay, rising edge | TD_IN+ | 12 | 25 | ns | 4 | ||
| IN+ to output propagation delay, falling edge | TD_IN+ | 12 | 25 | ns | 4 | ||
| IN- to output propagation delay, rising | TD_IN- | 12 | 25 | ns | 4 | ||
| IN- to output propagation delay, falling | TD_IN- | 12 | 25 | ns | 4 | ||
| Minimum input pulse width | TMIN_ON | 20 | 30 | ns | CLoad=1nF | 4 | |
| Thermal shutdown threshold, TJ rising | TSD | 170 | °C | TJ rising | 4 | ||
| Thermal shutdown hysteresis | 25 | °C | 4 | ||||
| Supply voltage VDD (absolute maximum) | VDD | -0.3 | 26 | V | 2 | ||
| Input voltage (absolute maximum) | IN+, IN- | -5 | 26 | V | 2 | ||
| Output voltage (absolute maximum) | OUT | -0.3 | 26 | V | 2 | ||
| Operating junction temperature (absolute maximum) | TJ | -40 | 150 | °C | 2 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 2 | ||
| Supply voltage range | VDD | 4.5 | 24 | V | 3 | ||
| Input voltage range | VIN+,IN- | -5 | 24 | V | 3 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 3 | ||
| ESD Human Body Model (HBM), all pins | VESD | -2 | 2 | kV | HBM, ANSI-JEDEC-JS-001-2014 | 3 | |
| ESD Charged Device Model (CDM), all pins | VESD | -1 | 1 | kV | CDM, ANSI-JEDEC-JS-002-2014 | 3 | |
| Junction to ambient thermal resistance (TSOT23-5) | RθJA | 89 | °C/W | 3 | |||
| Junction to case thermal resistance (TSOT23-5) | RθJC | 39 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
SCT51240TWBR - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
sct51240twbr-etched.step/sct51240twbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sct51240twbr.step/sct51240twbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (16 pp, sha256
2d92447ab0735a21, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SCT51240TWBR
**SCT** · Gate Drivers · TSOT-23-5L
SCT51240TWBR from SCT, in a TSOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Gate driver supply, must be decoupled by a ceramic capacitor (0.1 µF plus 1 µF or 10 µF recommended), with an operating supply range of 4.5 V to 24 V. |
| 2 | GND | power_in | Power ground, which must be soldered directly to ground planes for improved thermal performance and electrical contact. |
| 3 | IN+ | input | Non-inverting TTL-compatible logic input that floats low; it carries the PWM signal in non-inverting operation and is connected to VDD in inverting operation. |
| 4 | IN- | input | Inverting TTL-compatible logic input that floats low; it carries the PWM signal in inverting operation and is connected to GND in non-inverting operation. |
| 5 | OUT | output | Gate driver output, rail-to-rail, capable of 4 A peak source and 4 A peak sink current. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | TSOT-23-5L |
| Category | Motor Driver ICs |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage | VDD | 4.5 | | 24 | V | | 4 |
| Input UVLO, VDD rising | VDD_UVLO | | 4.2 | 4.5 | V | VDD rising | 4 |
| Input UVLO hysteresis | | | 300 | | mV | | 4 |
| Quiescent current | IQ | | 38 | | uA | IN+=IN-=GND, VDD=3.5V | 4 |
| Quiescent current | IQ | | 120 | | uA | IN+=IN-=GND, VDD=12V | 4 |
| Input+ logic high threshold | VIN+ | | 2.1 | 2.4 | V | | 4 |
| Input+ logic low threshold | VIN+ | 0.8 | 1 | | V | | 4 |
| Input+ hysteresis | VIN+_Hys | | 1.1 | | V | | 4 |
| Input- logic high threshold | VIN-_H | | 2.1 | 2.4 | V | | 4 |
| Input- logic low threshold | VIN-_L | 0.8 | 1 | | V | | 4 |
| Input- hysteresis | VIN-_Hys | | 1.1 | | V | | 4 |
| Output High Voltage (only PMOS ON) | VDD_VOH | | 150 | | mV | IOUT=10mA | 4 |
| Output Low Voltage | VOL | | 10 | | mV | IOUT=10mA | 4 |
| Output sink/source peak current | ISINK/SRC | | 4 | | A | CLoad=10nF, Fsw=1kHz | 4 |
| Output pull high resistance (only PMOS ON) | ROH | | 8.5 | | Ω | IOUT= - 10mA | 4 |
| Output pull low resistance | ROL | | 0.6 | | Ω | IOUT= 10mA | 4 |
| Output rising time | TR | | 9 | 20 | ns | CLoad=1nF | 4 |
| Output falling time | TF | | 6 | 20 | ns | CLoad=1nF | 4 |
| IN+ to output propagation delay, rising edge | TD_IN+ | 12 | | 25 | ns | | 4 |
| IN+ to output propagation delay, falling edge | TD_IN+ | 12 | | 25 | ns | | 4 |
| IN- to output propagation delay, rising | TD_IN- | 12 | | 25 | ns | | 4 |
| IN- to output propagation delay, falling | TD_IN- | 12 | | 25 | ns | | 4 |
| Minimum input pulse width | TMIN_ON | | 20 | 30 | ns | CLoad=1nF | 4 |
| Thermal shutdown threshold, TJ rising | TSD | | 170 | | °C | TJ rising | 4 |
| Thermal shutdown hysteresis | | | 25 | | °C | | 4 |
| Supply voltage VDD (absolute maximum) | VDD | -0.3 | | 26 | V | | 2 |
| Input voltage (absolute maximum) | IN+, IN- | -5 | | 26 | V | | 2 |
| Output voltage (absolute maximum) | OUT | -0.3 | | 26 | V | | 2 |
| Operating junction temperature (absolute maximum) | TJ | -40 | | 150 | °C | | 2 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 2 |
| Supply voltage range | VDD | 4.5 | | 24 | V | | 3 |
| Input voltage range | VIN+,IN- | -5 | | 24 | V | | 3 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 3 |
| ESD Human Body Model (HBM), all pins | VESD | -2 | | 2 | kV | HBM, ANSI-JEDEC-JS-001-2014 | 3 |
| ESD Charged Device Model (CDM), all pins | VESD | -1 | | 1 | kV | CDM, ANSI-JEDEC-JS-002-2014 | 3 |
| Junction to ambient thermal resistance (TSOT23-5) | RθJA | | 89 | | °C/W | | 3 |
| Junction to case thermal resistance (TSOT23-5) | RθJC | | 39 | | °C/W | | 3 |
## CAD (KiCad official)
- Symbol: `SCT51240TWBR`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-5`
- 3D model: TSOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `sct51240twbr-etched.step` / `sct51240twbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sct51240twbr.step` / `sct51240twbr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SCT datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918499700060160) (16 pp, sha256 `2d92447ab0735a21`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sct51240twbr-datasheet.pdf)