component
SCT2A23ASTER
Public Made by Adomby adom
SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSCT2A23ASTER
SCT · DC-DC Converters · ESOP-8
SCT2A23ASTER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground return. Electrically connected to the exposed thermal pad (pin 9). |
| 2 | VIN | power_in | Input supply voltage, 4.5V to 100V operating range (absolute max 105V). Connect a local bypass capacitor from VIN to GND; path from VIN to the high-frequency bypass capacitor and GND must be as short as possible. |
| 3 | EN | input | Enable input to the regulator, with internal pull-up current source. Float or tie to VIN to enable; pull below 1.23V to disable. A resistor divider from VIN to GND on EN programs the input UVLO threshold (VEN_H ≈ 1.24V, VEN_L ≈ 1.23V; IEN ≈ 17µA at 1.5V). |
| 4 | MODE | input | Light-load operation mode selection. Connect to VCC via a resistor for Forced PWM (FPWM, VMD_PWM ≥ 4.65V); ground for PFM (VMD_PFM ≤ 0.5V); leave floating for Ultrasonic Mode (USM, 1.5V-3.5V). |
| 5 | FB | input | Inverting input of the internal PWM comparator. Tap of an external feedback resistor divider from VOUT to GND sets the output voltage; regulated to VREF = 1.2V typical (1.176V-1.224V). |
| 6 | VCC | power_out | Output of the internal high-voltage LDO regulator (typ 7.3V), used to bias gate drivers and internal circuitry. Decouple with a capacitor larger than 1.0µF to GND. |
| 7 | BST | passive | Bootstrap supply for the high-side MOSFET gate driver. Connect a 0.1µF capacitor from BST to SW; the bootstrap cap is charged when the low-side MOSFET is on or SW is low. Absolute max BOOT-SW = 6V. |
| 8 | SW | power_out | Regulator switching output node between the internal high-side and low-side MOSFETs. Connect to the external power inductor. Absolute max -1V to 105V. |
| 9 | Thermal Pad | power_in | Exposed thermal pad, heat dissipation path of the die. Electrically connected to GND (pin 1); must be soldered to the PCB ground plane for proper operation and optimized thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SCT2A23ASTER
CAD (KiCad official)
- Symbol:
SCT2A23ASTER - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
sct2a23aster-etched.step/sct2a23aster-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sct2a23aster.step/sct2a23aster.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (24 pp, sha256
8741c4cd91d63328, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).