SCT2A10STER

@@ -26,7 +26,9 @@       "model_3d_step": "sct2a10ster.step",       "lbr": "sct2a10ster.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C509053"+    },     "pins": [       {         "number": "1",@@ -44,19 +46,19 @@         "number": "3",         "name": "EN",         "type": "input",-        "description": "Enable input with internal pull-up current source (~1-4µA). Pull below 1.1V to disable the converter; float or drive to VIN to enable. A resistor divider from VIN to GND on EN programs the input UVLO threshold (VEN_H≈1.21V, VEN_L≈1.05V)."+        "description": "Enable input with internal pull-up current source (~1-4\u00b5A). Pull below 1.1V to disable the converter; float or drive to VIN to enable. A resistor divider from VIN to GND on EN programs the input UVLO threshold (VEN_H\u22481.21V, VEN_L\u22481.05V)."       },       {         "number": "4",         "name": "RT",         "type": "input",-        "description": "Switching frequency programming pin. A resistor from RT to GND sets the internal oscillator frequency from 300kHz to 800kHz (e.g. RRT=500kΩ ≈500kHz). An external clock may be applied directly to RT/CLK to synchronize the internal PLL; if the external clock stops, operation reverts to the resistor-programmed frequency."+        "description": "Switching frequency programming pin. A resistor from RT to GND sets the internal oscillator frequency from 300kHz to 800kHz (e.g. RRT=500k\u03a9 \u2248500kHz). An external clock may be applied directly to RT/CLK to synchronize the internal PLL; if the external clock stops, operation reverts to the resistor-programmed frequency."       },       {         "number": "5",         "name": "FB",         "type": "input",-        "description": "Inverting input of the transconductance error amplifier. Connect the tap of the external output-to-GND resistor divider here; the device regulates FB to VREF = 0.8V typical (±1%)."+        "description": "Inverting input of the transconductance error amplifier. Connect the tap of the external output-to-GND resistor divider here; the device regulates FB to VREF = 0.8V typical (\u00b11%)."       },       {         "number": "6",@@ -68,7 +70,7 @@         "number": "7",         "name": "BST",         "type": "passive",-        "description": "Bootstrap supply for the high-side MOSFET gate driver. Connect a 0.1µF ceramic capacitor from BST to SW; the cap is recharged from an internal rail whenever the low-side MOSFET is on or SW is low. BOOT-SW absolute max is 6V."+        "description": "Bootstrap supply for the high-side MOSFET gate driver. Connect a 0.1\u00b5F ceramic capacitor from BST to SW; the cap is recharged from an internal rail whenever the low-side MOSFET is on or SW is low. BOOT-SW absolute max is 6V."       },       {         "number": "8",

@@ -63,6 +63,18 @@   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="9" x="0.0000" y="-0.0000" dx="2.4100" dy="3.3000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -71,7 +83,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="SCT2A10STER">@@ -86,7 +98,7 @@   <pin name="EN" x="-17.78" y="0" length="middle" direction="in"/>   <pin name="RT" x="-17.78" y="-2.54" length="middle" direction="in"/>   <pin name="FB" x="-17.78" y="-5.08" length="middle" direction="in"/>-  <pin name="Thermal Pad" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+  <pin name="Thermal_Pad" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>   <pin name="SW" x="17.78" y="0" length="middle" direction="out" rot="R180"/>   <pin name="BST" x="17.78" y="-2.54" length="middle" direction="pas" rot="R180"/>   <pin name="NC" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>@@ -106,12 +118,18 @@         <connect gate="G$1" pin="EN" pad="3"/>         <connect gate="G$1" pin="RT" pad="4"/>         <connect gate="G$1" pin="FB" pad="5"/>-        <connect gate="G$1" pin="Thermal Pad" pad="9"/>+        <connect gate="G$1" pin="Thermal_Pad" pad="9"/>         <connect gate="G$1" pin="SW" pad="8"/>         <connect gate="G$1" pin="BST" pad="7"/>         <connect gate="G$1" pin="NC" pad="6"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="SCT2A10STER" constant="no"/>+          <attribute name="MANUFACTURER" value="SCT" constant="no"/>+          <attribute name="LCSC_PN" value="C509053" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>